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參數資料
| 型號： | PCT1789N |
| 英文描述： | PCT303DL |
| 中文描述： | PCT303DL |
| 文件頁數： | 7/40頁 |
| 文件大小： | 632K |
| 代理商： | PCT1789N |
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PC-TEL, Inc.
16
1789N0DOCDAT01A-0399
PCT1789N DATA SHEET
303DL F
UNCTIONAL
D
ESCRIPTION
!
PRELIMINARY
PRELIMINARY
303DL F
UNCTIONAL
D
ESCRIPTION
The 303DL is an integrated chip-set that provides a low-
cost, isolated, silicon-based interface to the telephone
line. The 303DL saves cost and board area by
eliminating the need for a modem AFE or serial CODEC.
It also eliminates the need for an isolation transformer,
relays, opto-isolators, and a 2- to 4-wire hybrid. The
303DL solution requires only a few low-cost, discrete
components to achieve full compliance with FCC
Part 68 and JATE out-of-band noise requirements. See
Figure 2 on page 6 for a typical application circuit.
The 303DL North America/Japan DAA offers a number
of new features. These include operation from a single
3.3 V power supply, JATE (Japan) filter option, finer
resolution for both transmit and receive levels on AOUT
(call progress output), daisy-chaining for up to eight
devices, and an optional IIR filter. Table 7 summarizes
the new 303DL features.
Isolation Barrier
The 303DL achieves an isolation barrier through a low-
cost, high-voltage capacitor in conjunction with Silicon
Laboratories’ proprietary ISOcap signal processing
techniques. These techniques eliminate any signal
degradation due to capacitor mismatches, common
mode interference, or noise coupling. As shown in
Figure 2 on page 6, the C1, C2, and C4 capacitors
isolate the PCT303D (DSP side) from the PCT303L (line
side). All transmit, receive, control, and caller ID data
are communicated through this barrier.
The ISOcap inter-chip communication is disabled by
default. To enable it, the PDL bit in register 6 must be
cleared. No communication between the PCT303D and
PCT303L can occur until this bit is cleared. The clock
generator must be programmed to an acceptable
sample rate prior to clearing the PDL bit.
Off-Hook
The communication system generates an off-hook
command by applying logic 0 to the OFHK pin or writing
a logic 1 to bit 0 of control register 5. The OFHK pin must
be enabled by setting bit 1 (OHE) of register 5. With
OFHK at logic 0, the system is in an off-hook state. This
state is used to seize the line for incoming/outgoing calls
and can also be used for pulse dialing. With OFHK at
logic 1, negligible DC current flows through the
hookswitch. When a logic 0 is applied to the OFHK pin,
the hookswitch transistor pair, Q1 & Q2, turn on. The net
effect of the off-hook signal is the application of a
termination impedance across tip and ring and the flow
of DC loop current. The termination impedance has both
an AC and DC component.
The AC termination impedance is a 604-ohm resistor,
which is connected to the TX pin. The DC termination is
a 51-ohm resistor, which is connected to the DCT pin.
When executing an off-hook sequence, the 303DL
requires 4620/Fs clock cycles to complete the off-hook
and provide phone line data on the serial link. This
includes the 12/Fs filter group delay. If necessary, for
the shortest delay, a higher Fs may be established prior
to executing the off-hook, such as an Fs of 10.286 kHz.
Ring Detect
The ring signal enters the 303DL through low value
capacitors connected to Tip and Ring. RGDT is a
clipped, half-wave rectified version of the ringing
waveform. See Figure 7 on page 17 for a timing diagram
of the RGDT pin.
The integrated ring detect of the 303DL allows the
device to present the ring signal to the DSP, through the
serial port, with no additional signaling required. The
signal sent to the DSP is a clipped version of the original
ring signal. In addition, the 303DL passes through the
caller ID data unaltered.
The system can also detect an occurring ring by the
status of the RDT bit of register 5. This bit is a read-only
bit that is set when the line side device detects a ring
signal at RNG1 and RNG2. The RDT bit clears when the
system either goes off-hook or 4.5 to 9 seconds after the
last ring is detected.
Table 7 New 303DL Features
Category
Daisy-Chaining
Optional IIR Filter
Receive Gain
Transmit Attenuation
V
A
V
D
JATE Support
AOUT Levels (dB)
303DL
Up to 8 Devices
Yes
0, +3, +6, +9, +12 dB
0, –3, –6 –9, –12 dB
3.3 V
a
or 5 V
a.
The 3.3 V supply is internally generated by
an on-chip charge pump.
3.3 V or 5 V
Yes
0, –6, –12, mute
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