參數(shù)資料
型號(hào)： OX16PCI954-TQC60-A
廠商： Electronic Theatre Controls, Inc.
英文描述： Integrated Quad UART and PCI interface
中文描述： 綜合四UART和PCI接口
文件頁(yè)數(shù)： 9/72頁(yè)
文件大?。?/td> 656K
代理商： OX16PCI954-TQC60-A
Data Sheet Revision 1.3
Page 9
OX16PCI954
OXFORD SEMICONDUCTOR LTD.
Mode
00
01
10
11
Dir
1
Name
Description
Serial port pins
81, 78, 58, 53
N/A
O
RTS[3:0]#
Active-low modemrequest-to-send output. If automated
RTS#flow control is enabled, the RTS#pin is deasserted
and reasserted whenever the receiver FIFO reaches or falls
below the programmed thresholds, respectively.
Active-low modemclear-to-send input. If automated CTS#
flow control is enabled, upon deassertion of the CTS#pin,
the transmtter will complete the current character and enter
the idle mode until the CTS#pin is reasserted. Note: flow
control characters are transmtted regardless of the state of
the CTS#pin.
Active-low modemdata-set-ready input. If automated DSR#
flow control is enabled, upon deassertion of the DSR#pin,
the transmtter will complete the current character and enter
the idle mode until the DSR#pin is reasserted. Note: flow
control characters are transmtted regardless of the state of
the DSR#pin
External receiver clock for isochronous applications. The
Rx_Clk_In is selected when CKS[1:0] = ‘01’.
Active-low modemRing-Indicator input
External transmtter clock. This clock can be used by the
transmtter (and indirectly by the receiver) when CKS[6]=’1’.
Crystal oscillator output
Crystal oscillator input or external clock pin. Maximum
frequency 60MHz
83, 76, 60, 51
N/A
I
CTS[3:0]#
84, 75, 61, 50
N/A
I
I
DSR[3:0]#
Rx_Clk_In[3:0]
86, 73, 67, 48
N/A
I
I
RI[3:0]#
Tx_Clk_In[3:0]
64
63
N/A
N/A
O
I
XTLO
XTLI
8-bit local bus
71
N/A
O
UART_Clk_Out
Buffered crystal output. This clock can drive external UARTs
connected to the local bus. Can be enabled / disabled by
software.
Local bus active-high reset
Local bus active-low reset
Local bus data out enable. This pin can be used by external
transceivers; it is high when LBD[7:0] are in output mode and
low when they are in input mode.
Buffered PCI clock. Can be enabled / disabled by software
Local bus active-low Chip-Select (Intel mode)
Local bus active-low Data-Strobe (Motorola mode)
Local Bus active-low write-strobe (Intel mode)
Local Bus Read-not-Write control (Motorola mode)
Local Bus active-low read-strobe (Intel mode)
Permanent high impedance (Motorola mode)
Local bus address signals
122
123
N/A
N/A
O
O
O
LBRST
LBRST#
LBDOUT
102
N/A
109
114-7
N/A
N/A
O
O
O
O
O
O
Z
O
LBCLK
LBCS[3:0]#
LBDS[3:0]#
LBWR#
LBRDWR#
LBRD#
Hi-Z
LBA[7:0]
112
N/A
113
N/A
105-8
118-21
92-5
98-101
N/A
N/A
See
32-bit
Local
bus
I/O
LBD[7:0]
Local bus data signals
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