參數(shù)資料
型號(hào)： OX16PCI954-TQC60-A
廠商： Electronic Theatre Controls, Inc.
英文描述： Integrated Quad UART and PCI interface
中文描述： 綜合四UART和PCI接口
文件頁數(shù)： 33/72頁
文件大?。?/td> 656K
代理商： OX16PCI954-TQC60-A
Data Sheet Revision 1.3
Page 33
OX16PCI954
OXFORD SEMICONDUCTOR LTD.
Register
Name
SPR
Offset
10
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Indexed Control Register Set
ICR
Read
Enable
Level
Enable
ACR
0x00
R/W
Addit-
ional
Status
Enable
950
Trigger
DTR definition and
control
Auto
DSR
Flow
Control
Enable
Tx
Disable
Rx
Disable
CPR
0x01
R/W
5 Bit “integer” part of
clock prescaler
Unused
3 Bit “fractional” part of
clock prescaler
4 Bit N-times clock
selection bits [3:0]
0
TCR
0x02
R/W
CKS
0x03
R/W
Tx 1x
Mode
Unused
Tx CLK
Select
BDOUT
on DTR
DTR 1x
Tx CLK
Rx 1x
Mode
Receiver
Clock Sel[1:0]
TTL
0x04
R/W
Transmtter Interrupt Trigger Level (0-127)
RTL
0x05
R/W
Unused
Receiver Interrupt Trigger Level (1-127)
FCL
0x06
R/W
Unused
Automatic Flow Control Lower Trigger Level (0-127)
FCH
0x07
R/W
Unused
Automatic Flow Control Higher Trigger level (1-127)
ID1
0x08
R
Hardwired ID byte 1 (0x16)
ID2
0x09
R
Hardwired ID byte 1 (0xC9)
ID3
0x0A
R
Hardwired ID byte 1 (0x50)
REV
0x0B
R
Hardwired revision byte (0x01)
CSR
0x0C
W
Writing 0x00 to this register will
reset the UART (Except the CKS register)
9
th
Bit
SChar 4
SChar 3
SIN
wakeup
disable
Disable
FCR[5]
FCR[4]
0
0
NMR
0x0D
R/W
Unused
9
th
Bit
9
th
Bit
SChar 2
DCD
Wakeup
disable
FCR[3]
0
9
th
Bit
SChar 1
Trailing
RI edge
disable
FCR[2]
0
9
th
-bit Int.
En.
DSR
Wakeup
disable
FCR[1]
0
9 Bit
Enable
CTS
Wakeup
disable
FCR[0]
Good
data
status
MDM
0x0E
R/W
0
0
Modem
Wakeup
RFC
GDS
0X0F
0X10
R
R
FCR[7]
0
FCR[6]
0
Table 17: Indexed Control Register Set
Note 10: The SPR offset column indicates the value that must be written into SPR prior to reading / writing any of the Indexed Control Registers via ICR.
Offset values not listed in the table are reserved for future use and must not be used.
To read or write to any of the Indexed Controlled Registers use the following procedure:
Writing to ICR registers:
Ensure that the last value written to LCR was not 0xBF (reserved for 650 compatible register access value).
Write the desired offset to SPR (address 111b).
Write the desired value to ICR (address 101b).
Reading fromICR registers:
Ensure that the last value written to LCR was not 0xBF (see above).
Write 0x00 offset to SPR to select ACR.
Set bit 6 of ACR (ICR read enable) by writing x1xxxxxxb to address 101b. Ensure that other bits in ACR are not changed.
(Software drivers should keep a copy of the contents of the ACR elsewhere since reading ICR involves overwriting ACR!)
Write the desired offset to SPR (address 111b).
Read the desired value fromICR (address 101b).
Write 0x00 offset to SPR to select ACR.
Clear bit 6 of ACR bye writing x0xxxxxxb to ICR, thus enabling access to standard registers again.
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