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參數(shù)資料
| 型號： | OX16PCI954-TQC60-A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Integrated Quad UART and PCI interface |
| 中文描述： | 綜合四UART和PCI接口 |
| 文件頁數(shù)： | 20/72頁 |
| 文件大小： | 656K |
| 代理商： | OX16PCI954-TQC60-A |
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Data Sheet Revision 1.3
Page 20
OX16PCI954
OXFORD SEMICONDUCTOR LTD.
Bits
17:16
Description
MIO8 Configuration Register.
00 -> MIO8 is a non-inverting input pin
01 -> MIO8 is an inverting input pin
10 -> MIO8 is an output pin driving ‘0’
11 -> MIO8 is an output pin driving ‘1’
MIO9 Configuration Register.
00 -> MIO9 is a non-inverting input pin
01 -> MIO9 is an inverting input pin
10 -> MIO9 is an output pin driving ‘0’
11 -> MIO9 is an output pin driving ‘1’
MIO10 Configuration Register.
00 -> MIO10 is a non-inverting input pin
01 -> MIO10 is an inverting input pin
10 -> MIO10 is an output pin driving ‘0’
11 -> MIO10 is an output pin driving ‘1’
MIO11 Configuration Register.
00 -> MIO11 is a non-inverting input pin
01 -> MIO11 is an inverting input pin
10 -> MIO11 is an output pin driving ‘0’
11 -> MIO11 is an output pin driving ‘1’
Reserved
Read/Write
EEPROM
W
Reset
00
PCI
RW
19:18
W
RW
00
21:20
W
RW
00
23:22
W
RW
00
31:24
-
R
00h
6.4.3
The Local Bus Timng Parameter registers (LT1 and LT2) define the operation and timng parameters used by the Local Bus.
The timng parameters are programmed in 4-bit registers to define the assertion/de-assertion of the Local Bus control signals.
The value programmed in these registers defines the number of PCI clock cycles after a Reference Cycle when the events
occur, where the reference Cycle is defined as two clock cycles after the master asserts the IRDY#signal. The following
arrangement provides a flexible approach for users to define the desired bus timng of their peripheral devices. The timngs refer
to I/O or Memory mapped access to BAR0 and BAR1 of Function1.
Bits
Description
3:0
Read Chip-select Assertion (Intel-type interface). Defines the number of
clock cycles after the Reference Cycle when the LBCS[3:0]#pins are
asserted (low) during a read operation fromthe Local Bus.
1
These bits are unused in Motorola-type interface.
7:4
Read Chip-select De-assertion (Intel-type interface). Defines the number
of clock cycles after the Reference Cycle when the LBCS[3:0]#pins are
de-asserted (high) during a read fromthe Local Bus.
1
These bits are unused in Motorola-type interface.
11:8
Write Chip-select Assertion (Intel-type interface). Defines the number of
clock cycles after the Reference Cycle when the LBCS[3:0]#pins are
asserted (low) during a write operation to the Local Bus.
1
These bits are unused in Motorola-type interface.
Local Bus Timing Parameter register 1 ‘LT1’ (Offset 0x08):
Read/Write
EEPROM
W
Reset
0h
PCI
RW
W
RW
3h
(2h for
parallel port)
W
RW
0h
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相關(guān)代理商/技術(shù)參數(shù) |
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