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參數(shù)資料
| 型號： | OX16PCI954-TQC60-A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Integrated Quad UART and PCI interface |
| 中文描述： | 綜合四UART和PCI接口 |
| 文件頁數(shù)： | 23/72頁 |
| 文件大小： | 656K |
| 代理商： | OX16PCI954-TQC60-A |
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LT2[15:0] enable the card designer to control the data bus during the idle periods. The default values will configure the Local Bus
data pins to remain forcing (LT2[7:4] = Fh). LT[15:8] is programmed to place the bus in high-impedance at the beginning of a
read cycle and set it back to forcing at the end of the read cycle. For systems that require the data bus to stay in high-
impedance, the card designer should write an appropriate value in the range of 0h to Ah to LT2[7:4]. This will place the data bus
in high impedance at the end of the write cycle. Whenever the value programmed in LT2[7:4] does not equal Fh, the Local Bus
controller will ignore the setting of LT2[15:8] as the data bus will be high-impedance outside write cycles. In this case the card
designer should place external pull-ups on the data bus pins LBD[7:0] (or LBD[32:0] in 32-bit mode).
While the configuration data is read fromthe external EEPROM the LBD pins remain in the high-impedance state.
The timng registers define the Local Bus timng parameters based on signal changes relative to a reference cycle which is
defined as two PCI clock cycles after IRDY#is asserted for the first time in a frame. The following parameters are fixed relative to
the reference cycle.
The Local Bus address pins (LBA[7:0] in 8-bit Local Bus, LBA[15:0] in 32-bit Local Bus) are asserted during the reference cycle.
In a write operation, the Local Bus data is available during the reference cycle, however I/O buffers change direction as
programmed in LT2[3:0].
In a Motorola type bus write operation, the Read-not-Write pin (LBRDWR#) is asserted (low) during the reference cycle. In a read
cycle this pin remains high throughout the duration of the operation.
The default settings in LT1 & LT2 registers provide one PCI clock cycle for address and chip-select to control signal set-up time,
one clock cycle for address and chip-select fromcontrol signal hold time, two clock cycles of pulse duration for read and write
control signals and one clock cycle for data bus hold time. These parameters are acceptable for using external OX16C950,
OX16C952 and OX16C954 devices connected to the Local Bus, in Intel mode. Some redefinition will be required if the bus is to
be operated in Motorola mode.
The user should take great care when programmng the Local Bus timng parameters. For example defining a value for chip-
select assertion which is larger that the value defined for chip-select de-assertion or defining a chip-select assertion value which
is greater than control signal assertion will result in obvious invalid local Bus cycles.
Data Sheet Revision 1.3
Page 23
OX16PCI954
OXFORD SEMICONDUCTOR LTD.
6.4.5
The receiver FIFO level of all internal UARTs are shadowed in Local configuration registers as follows:
Bits
Description
7:0
UART0 Receiver FIFO Level (RFL[7:0])
15:8
UART1 Receiver FIFO Level (RFL[7:0])
23:16
UART2 Receiver FIFO Level (RFL[7:0])
31:24
UART3 Receiver FIFO Level (RFL[7:0])
UART Receiver FIFO Levels ‘URL’ (Offset 0x10)
Read/Write
EEPROM
-
-
-
-
Reset
0x00h
0x00h
0x00h
0x00h
PCI
R
R
R
R
6.4.6
The transmtter FIFO level of all internal UARTs are shadowed in Local configuration registers as follows:
Bits
Description
7:0
UART0 Transmtter FIFO Level (TFL[7:0])
15:8
UART1 Transmtter FIFO Level (TFL[7:0])
23:16
UART2 Transmtter FIFO Level (TFL[7:0])
31:24
UART3 Transmtter FIFO Level (TFL[7:0])
UART Transmitter FIFO Levels ‘UTL’ (Offset 0x14)
Read/Write
EEPROM
-
-
-
-
Reset
0x00h
0x00h
0x00h
0x00h
PCI
R
R
R
R
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