參數(shù)資料
型號(hào)： OX16PCI954-TQC60-A
廠商： Electronic Theatre Controls, Inc.
英文描述： Integrated Quad UART and PCI interface
中文描述： 綜合四UART和PCI接口
文件頁數(shù)： 24/72頁
文件大?。?/td> 656K
代理商： OX16PCI954-TQC60-A
Data Sheet Revision 1.3
Page 24
OX16PCI954
OXFORD SEMICONDUCTOR LTD.
6.4.7
The UART Interrupt Source register is described below:
Bits
Description
5:0
UART0 Interrupt Source Register (ISR[5:0])
11:6
UART1 Interrupt Source Register (ISR[5:0])
17:12
UART2 Interrupt Source Register (ISR[5:0])
23:18
UART3 Interrupt Source Register (ISR[5:0])
26:24
Reserved
27
UART0 Good-Data Status
28
UART1 Good-Data Status
29
UART2 Good-Data Status
30
UART3 Good-Data Status
31
Global Good-Data Status. This bit is the logical AND of bits 27 to 30, i.e.
it is set if Good-Data Status of all internal UARTs is set.
Good-Data status for a given internal UART is set when all of the following conditions are met:
ISR reads a level0 (no-interrupt pending), a level 2a (receiver data available, a level 2b (receiver time-out) or a level 3
(transmtter THR empty) interrupt
LSR[7] is clear so there is no parity error, framng error or break in the FIFO
LSR[1] is clear so no over-run error has occurred
If the device driver software reads the receiver FIFO levels (URL) followed by this register, then if Good-Data status for a given
channel is set, the driver can remove the number of bytes indicated by the FIFO level without the need to read the line status
register for that channel. This feature enhances the driver efficiency.
For a given channel, if the Good-Data status bit is
not
set, then the software driver should examne the corresponding ISR bits.
For example if bit 29 is low, then the driver should examne bits 17 down to 12 to obtain the ISR[5:0] for UART2. If the ISR
indicates a level 4 or higher interrupt, the interrupt is due to a change in the state of modemlines or detection of flow control
characters. The device driver-software should then take appropriate measures as would in any other 550/950 driver. When ISR
indicates a level 1 (receiver status) interrupt then the driver can examne the Line Status Register (LSR) of the relevant channel.
Since reading the LSR clears LSR[7], the device driver-software should either flush or empty the contents of the receiver FIFO,
otherwise the Good-Data status will no longer be valid.
The UART Receiver FIFO Level (URL), UART Transmtter FIFO Level (UTL), UART Interrupt Source register (UIS) and Global
Interrupt Status register (GIS) are allocated adjacent address offsets (10h to 1Ch) in the Base Address Register. The device
driver-software can read all of the above registers in single burst read operation. The location offset of the registers are such that
the FIFO levels are usually read before the status registers so that the status of the N characters indicated in the receiver FIFO
levels are valid.
UART Interrupt Source Register ‘UIS’ (Offset 0x18)
Read/Write
EEPROM
-
-
-
-
-
-
-
-
-
-
Reset
01h
01h
01h
01h
00h
PCI
R
R
R
R
R
R
R
R
R
R
1
1
1
1
1
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