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| 型號(hào)： | OX16PCI954-TQC60-A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Integrated Quad UART and PCI interface |
| 中文描述： | 綜合四UART和PCI接口 |
| 文件頁(yè)數(shù)： | 54/72頁(yè) |
| 文件大?。?/td> | 656K |
| 代理商： | OX16PCI954-TQC60-A |
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9.3
Data Sheet Revision 1.3
Page 54
OX16PCI954
OXFORD SEMICONDUCTOR LTD.
Register Description
The parallel port registers are described below. (NB it is assumed that the upper block is placed 400h above the lower block).
Register
Name
Offset
SPP (Compatibility Mode) Registers
PDR
000h
R/W
DSR
(EPP mode)
(Other modes)
001h
R
nBUSY
ACK#
DCR
002h
R/W
0
0
DIR
EPPA
1
003h
R/W
EPPD1
1
004h
R/W
EPPD2
1
005h
R/W
EPPD3
1
006h
R/W
EPPD4
1
007h
R/W
-
400h
-
-
401h
-
ECR
402h
R/W
Mode[2:0]
-
403h
-
Address
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Parallel Port Data Register
SLCT
001h
R
nBUSY
ACK#
PE
ERR#
INT#
1
Timeout
PE
SLCT
INT_EN
EPP Address Register
EPP Data 1 Register
EPP Data 2 Register
EPP Data 3 Register
EPP Data 4 Register
Reserved
Reserved
Reserved – Must write ‘00001’
Reserved
ERR#
nSLIN#
INT#
INIT#
1
1
nAFD#
nSTB#
Table 30: Parallel port register set
Note 1 : These registers are only available in EPP mode.
Note 2 : Prefix ‘n denotes that a signal is inverted at the connector. Suffix ‘# denotes active-low signalling
The reset state of PDR, EPPA and EPPD1-4 is not determnable (i.e. 0xXX). The reset value of DSR is ‘XXXXX111’. DCR and
ECR are reset to ‘0000XXXX’ and ‘00000001’ respectively.
9.3.1
PDR is located at offset 000h in the lower block. It is the
standard parallel port data register. Writing to this register
in mode 000 will drive data onto the parallel port data lines.
In all other modes the drivers may be tri-stated by setting
the direction bit in the DCR. Reads fromthis register return
the value on the data lines.
Parallel port data register ‘PDR’
9.3.2
DSR is located at offset 001h in the lower block. It is a read
only register showing the current state of control signals
fromthe peripheral. Additionally in EPP mode, bit 0 is set
to ‘1’ when an operation times out (see section 9.1.3)
DSR[0]:
EPP mode: Timeout
logic 0
Timeout has not occurred.
logic 1
Timeout has occurred (Reading this bit clears it).
Other modes: Unused
This bit is permanently set to 1.
DSR[1]: Unused
This bit is permanently set to 1.
Device status register ‘DSR’
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