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參數(shù)資料
| 型號： | OX16PCI954-TQC60-A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Integrated Quad UART and PCI interface |
| 中文描述： | 綜合四UART和PCI接口 |
| 文件頁數(shù)： | 62/72頁 |
| 文件大?。?/td> | 656K |
| 代理商： | OX16PCI954-TQC60-A |
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Data Sheet Revision 1.3
Page 62
OX16PCI954
OXFORD SEMICONDUCTOR LTD.
Symbol
t
ref
t
za
t
ads
t
zrds1
t
zrds2
vt
drd
t
zd1
Parameter
IRDY# falling to reference LBCLK
Reference LBCLK to Address Valid
Address Valid to LBDS#falling
Reference LBCLK to LBDS#falling
Reference LBCLK to LBDS#rising
Data bus floating to LBDS#falling
Reference LBCLK to data bus floating at the start of the read
transaction
Reference LBCLK to data bus driven by OX16PCI954 at the end of the
read transaction
Data bus valid to LBDS#rising
Data bus valid after LBDS#rising
Min
Nomnally 2 PCI clock cycles
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Max
Units
ns
ns
ns
ns
ns
ns
t
zd2
TBD
TBD
ns
t
sd
t
hd
TBD
TBD
TBD
TBD
ns
ns
Table 44: Read operation from Motorola-type Local Bus
Symbol
t
ref
t
za
t
ads
t
zw1
t
zw2
t
wds
t
dsw
t
zwds1
t
zwds2
t
zdv
t
zdf
t
dsdi
Parameter
IRDY# falling to reference LBCLK
Reference LBCLK to Address Valid
Address Valid to LBDS#falling
Reference LBCLK to LBRDWR#falling
Reference LBCLK to LBRDWR#rising
LBRDWR#falling to LBDS#falling
LBDS#rising to LBRDWR#rising
Reference LBCLK to LBDS#falling
Reference LBCLK to LBDS#rising
Reference LBCLK to data bus valid
Reference LBCLK to data bus high-impedance
LBDS#rising to data bus invalid
Min
Nomnally 2 PCI clock cycles
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 45: Write operation to Motorola-type Local Bus
13.3 Serial ports
Isochronous (x1 Clock) Timing:
Symbol
Parameter
t
irs
SIN set-up time to Isochronous input clock ‘Rx_Clk_In rising
1
t
irh
SIN hold time after Isochronous input clock ‘Rx_Clk_In rising
1
t
its
SOUT valid after Isochronous output clock ‘Tx_Clk_Out’ falling
1
Min
TBD
TBD
TBD
Max
TBD
TBD
TBD
Units
ns
ns
ns
Table 46: Isochronous mode timing
Note 1:
In Isochronous mode, transmtter data is available after the falling edge of the x1 clock and the receiver data is sampled using the rising edge of the
x1 clock. The systemdesigner is should ensure that mark-to-space ratio of the x1 clock is such that the required set-up and hold timng constraint
are met. One way of achieving this is to choose a crystal frequency which is twice the required data rate and then divide the clock by two using the
on-board prescaler. In this case the mark-to-space ratio is 50/50 for the purpose of set-up and hold calculations.
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