參數(shù)資料
型號(hào)： OX16PCI954-TQC60-A
廠商： Electronic Theatre Controls, Inc.
英文描述： Integrated Quad UART and PCI interface
中文描述： 綜合四UART和PCI接口
文件頁(yè)數(shù)： 18/72頁(yè)
文件大?。?/td> 656K
代理商： OX16PCI954-TQC60-A
6.4
Data Sheet Revision 1.3
Page 18
OX16PCI954
OXFORD SEMICONDUCTOR LTD.
Accessing Local configuration registers
The local configuration registers are a set of device specific registers which can be accessed fromeither function. They are
mapped to the I/O and memory addresses set up in BAR2 and BAR3 of each function, with the offsets defined for each register.
Access is limted to byte only for I/O accesses; memory accesses can also be word or dword accessed, however on little-endian
systems such as Intel 80x86 the byte order will be reversed.
6.4.1
This register defines control of ancillary functions such as Power Management, external clock reference signals and the serial
EEPROM. The individual bits are described below.
Bits
Description
1:0
Mode. These bits return the state of the Mode[1:0] pins.
2
Enable UART clock output. When this bit is set, the buffered UART clock
output pin (UART_CLK_Out) is active. When low UART_CLK_Out is
permanently low.
4:3
Endian Byte-Lane Select for memory access to 8-bit peripherals.
00 = Select Data[7:0] 10 = Select Data[23:16]
01 = Select Data[15:8] 11 = Select Data[31:24]
Memory access to OX16PCI954 is always DWORD aligned. When
accessing 8-bit regions like the internal UARTs, the 8-bit Local Bus and
the parallel port, this option selects the active byte lane. As both PCI and
PC architectures are little endian, the default value will be used by
systems, however, some non-PC architectures may need to select the
byte lane. These bits are ignored in 32-bit Local Bus.
6:5
Power-down filter time. These bits define a value of an internal filter time
for power-down interrupt request in power management circuitry in
Function0. Once Function0 is ready to go into power down mode,
OX16PCI954 will wait for the specified filter time and if Function0 is still
in power-down request mode, it can assert a PCI interrupt (see section
6.6).
00 = power-down request disabled
01 = 4 seconds
11 = 518 seconds
7
Function1 MIO2_PME Enable. A value of ‘1’ enables MIO2 pin to set the
PME_Status in PMCSR register, and hence assert the PME#pin if
enabled. A value of ‘0’ disables MIO2 fromsetting the PME_Status bit
(see section 6.6).
23:8
Reserved. These bits are used for test purposes. The device driver must
write zeros to these bits.
24
EEPROMClock. For PCI read or write to the EEPROM, toggle this bit to
generate an EEPROMclock (EE_CK pin).
25
EEPROMChip Select. When 1 the EEPROMchip-select pin EE_CS is
activated (high). When 0 EE_CS is de-active (low).
26
EEPROMData Out. For writes to the EEPROM this output bit is the
input-data of the EEPROM. This bit is output on EE_DO and clocked into
the EEPROMby EE_CK.
27
EEPROMData In. For reads fromthe EEPROM this input bit is the
output-data of the EEPROMconnected to EE_DI pin.
28
EEPROMValid. A 1 indicates that a valid EEPROMprogramis present
29
Reload configuration fromEEPROM. Writing a 1 to this bit re-loads the
configuration fromEEPROM. This bit is self-clearing after EEPROMread
30
Reserved
31
Reserved
Local Configuration and Control register ‘LCC’ (Offset 0x00)
Read/Write
EEPROM
-
W
Reset
XX
0
PCI
R
RW
W
RW
00
W
RW
00
10 = 129 seconds
W
RW
0
-
R
0000h
-
W
0
-
W
0
-
W
0
-
R
X
-
-
R
W
X
0
-
-
-
R
0
0
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