參數(shù)資料
型號(hào)： OX16PCI954-TQC60-A
廠商： Electronic Theatre Controls, Inc.
英文描述： Integrated Quad UART and PCI interface
中文描述： 綜合四UART和PCI接口
文件頁(yè)數(shù)： 10/72頁(yè)
文件大小： 656K
代理商： OX16PCI954-TQC60-A
Data Sheet Revision 1.3
Page 10
OX16PCI954
OXFORD SEMICONDUCTOR LTD.
Mode
00
01
10
11
Dir
1
Name
Description
Parallel port
N/A
122
N/A
I
I
I
I
I
ACK#
INTR#
PE
BUSY
WAIT#
Acknowledge (SPP mode). ACK#is asserted (low) by the
peripheral to indicate that a successful data transfer has
taken place.
Identical function to ACK#(EPP mode).
Paper Empty. Activated by printer when it runs out of paper.
Busy (SPP mode). BUSY is asserted (high) by the peripheral
when it is not ready to accept data
Wait (EPP mode). Handshake signal for interlocked IEEE
1284 compliant EPP cycles.
Select (SPP mode). Asserted by host to select the peripheral
Address strobe (EPP mode) provides address read and write
strobe
Peripheral selected. Asserted by peripheral when selected.
Error. Held low by the peripheral during an error condition.
Initialize (SPP mode). Commands the peripheral to initialize.
Initialize (EPP mode). Identical function to SPP mode.
Auto Feed (SPP mode, open-drain)
Data strobe (EPP mode) provides data read and write strobe
Strobe (SPP mode). Used by peripheral to latch data
currently available on PD[7:0]
Write (EPP mode). Indicates a write cycle when low and a
read cycle when high
Parallel data bus
N/A
N/A
121
120
N/A
N/A
N/A
108
N/A
OD
O
SLIN#
ADDRSTB#
N/A
N/A
N/A
119
118
107
N/A
N/A
N/A
I
I
SLCT
ERR#
INIT#
INIT#
AFD#
DATASTB#
STB#
WRITE#
OD
O
OD
O
OD
O
N/A
106
N/A
N/A
105
N/A
N/A
32-bit Local bus
See
8-bit
local
bus
Bus
N/A
I/O
PD[7:0]
N/A
N/A
N/A
122
123
102
O
O
O
LBRST
LBRST#
LBDOUT
Local bus active-high reset
Local bus active-low reset
Local bus data out enable. This pin can be used by external
transceivers; it is high when LBD[7:0] are in output mode and
low when they are in input mode.
Buffered PCI clock. Can be enabled / disabled by software
Local bus active-low Chip-Select (Intel mode)
Local bus active-low Data-Strobe (Motorola mode)
Local Bus active-low write-strobe (Intel mode)
Local Bus Read-not-Write control (Motorola mode)
Local Bus active-low read-strobe (Intel mode)
Permanent high impedance (Motorola mode)
Local bus address signals
N/A
N/A
109
114-7
O
O
O
O
O
O
Z
O
LBCLK
LBCS[3:0]#
LBDS[3:0]#
LBWR#
LBRDWR#
LBRD#
Hi-Z
LBA[12:0]
N/A
112
N/A
113
N/A
76-9, 105-8, 118-
121
47-55, 58-61, 66-68,
80-87, 92-95,98-101
N/A
I/O
LBD[31:0]
Local bus data signals
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