參數(shù)資料
型號(hào)： NCT7491RQR2G
廠商： ON Semiconductor
文件頁(yè)數(shù)： 65/80頁(yè)
文件大小： 844K
描述： IC REMOTE THERMAL MONITOR 24QSOP
標(biāo)準(zhǔn)包裝： 2,500
系列： *
NCT7491
http://onsemi.com
65
Table 97. REGISTER 0x81  Interrupt Status Register 4 (PowerOn Default = 0x00)
Bit
Description
R/W
Name
<6>
SMBCNT
R
Logic 1 indicates that the byte count returned by the SMBus Master Block Read is too low. If the
PCH temperature only is required then the returned byte count should be 2 or greater. If DIMM
temperatures are being read from the PCH then the returned byte count should be 9 or greater.
<7>
V
TT
R
A logic 1 indicates that the V
TT
 high or low limit has been exceeded. This bit is cleared on a read
of the status register only if the error condition has subsided.
Table 98. REGISTER 0x82  Interrupt Mask Register 3 (PowerOn Default = 0x00)
Bit
Name
R/W
Description
<0>
PECI0
R/W
A logic 1 masks SMBALERT
 assertions for outoflimit conditions on PECI0.
<1>
DATA
R/W
A logic 1 masks SMBALERT
 assertions for PECI Data errors. This also disables the fan override
function for PECI errors.
<2>
COMM
R/W
A logic 1 masks SMBALERT
 assertions for PECI communications errors. This also disables the
fan override function for PECI errors.
<3>
OVT
R/W
OVT = 1 masks SMBALERT
 for over temperature THERM
 conditions.
<6:4>
RES
R/W
Reserved
<7>
R
Reserved
NOTE:   If the mask bits in register 0x82 are set it is also necessary to set the OOL mask bit in register 0x75 to ensure the SMBALERT
output is not asserted.
Table 99. REGISTER 0x83  Interrupt Mask Register 4 (PowerOn Default = 0x00)
Bit
Name
R/W
Description
<0>
PCC
R/W
Logic 1 masks ALERT
 assertions for PECI completion codes.
<1>
TTS
R/W
Logic 1 masks assertions for THERM Timer status bit
<2>
GCOMM
R/W
Logic 1 masks the GCOMM PECI status bit
<3>
PECI1
R/W
A logic 1 masks ALERT
 assertions for outoflimit conditions on PECI1.
<4>
PECI2
R/W
A logic 1 masks ALERT
 assertions for outoflimit conditions on PECI2.
<5>
PECI3
R/W
A logic 1 masks ALERT
 assertions for outoflimit conditions on PECI3.
<6>
SMBCNT
R/W
Logic 1 masks ALERT
 assertions for incorrect byte count values returned by the Block Read command
<7>
V
TT
R/W
A logic 1 masks ALERT
 assertions for outoflimit conditions on V
TT
.
NOTE:   If the mask bits in register 0x83 are set it is also necessary to set the OOL mask bit in register 0x82 to ensure the SMBALERT
output is not asserted.
Table 100. V
TT
 LOW LIMIT REGISTER
Register Address
R/W
Description
PowerOn Default
0x84
R/W
V
TT
 Low Limit
0x00
Table 101. REGISTER 0x85  GPIO Config2 (PowerOn Default = 0x80)
Bit
Name
R/W
Description
<4:0>
Reserved
<5>
GPIO3
R/W
If GPIO3 is set to input, this bit reflects the state of the pin. If GPIO3 is configured as an
output, writing to this register asserts the output high or low depending on the polarity.
<6>
GPIO3 POL
R/W
GPIO3 polarity bit. Set to 0 for active low. Set to1 for active high.
<7>
GPIO3 DIR
R/W
GPIO3 direction bit. Set to 1 for GPIO3 to act as an input, set to 0 for GPIO3 to act as an
output, OOL must also be masked.
Table 102. V
TT
 HIGH LIMIT REGISTER
Register Address
R/W
Description
PowerOn Default
0x86
R/W
V
TT
 High Limit
0xFF
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