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參數(shù)資料
| 型號： | NCT7491RQR2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 17/80頁 |
| 文件大?。?/td> | 844K |
| 描述： | IC REMOTE THERMAL MONITOR 24QSOP |
| 標(biāo)準包裝： | 2,500 |
| 系列： | * |
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NCT7491
http://onsemi.com
17
PECI Registers
The registers relating to the operation of the PECI 3.0
interface are as follows:
Enabling the Interface:
" PECI Monitor, 0x40 bit 4
Setting PECI Monitor to 1 enables the PECI temperature
monitoring loop. This will be automatically enabled on
power up if the V
TT
and V
CCP
voltages have exceeded preset
thresholds and any PECI 3.0 enabled processors have been
automatically detected.
NOTE: The PDET bit (bit <0> 0x37) must also be set
for correct operation.
Detected number of CPUs:
" CPU Count, 0x88 bits <7:6>
" PDET, 0x37 <0>
CPU Count indicates the number of populated CPUs.
CPUs are automatically detected on power up by the
NCT7491 and the number found is set here. The number can
be overwritten by the user and sets the number of CPUs to
be included in the temperature monitoring loop. The number
of CPUs is 1 to 4, and the format is as shown in Table 10.
PDET is set if at least one PECI enabled processor is
detected. If it is not automatically set then it must be set by
the user.
Table 10. CPU COUNT
0x88 <7:6>
CPU Count
<00>
1
<01>
2
<10>
3
<11>
4
Domain Count bits:
" DOM0, 0x36 bit 3
" DOM1, 0x88 bit 5
" DOM2, 0x88 bit 4
" DOM3, 0x88 bit 3
These bits indicate the number of supported domains per
CPU (0 = 1 domain, 1 = 2 domains). THE NCT7491
automatically detects these values on power up and sets the
appropriate bits. They can be overwritten by the user.
PECI Interval:
" PECI Update Rate, 0x37 bits <5:4>
This determines the rate at which the PECI temperature
registers are updated.
Table 11. UPDATE RATE
0x37 <5:4>
PECI Update Rate
<00>
1/sec
<01>
2/sec
<10>
5/sec
<11>
10/sec
PECI CPU Addresses:
" PECI0 CPU Address, 0x00
" PECI1 CPU Address, 0x01
" PECI2 CPU Address, 0x02
" PECI3 CPU Address, 0x03
These are the addresses used to access each CPU on the
PECI interface and are automatically populated by the
NCT7491 on power up. The values can be overwritten by the
user.
PECI Temperature Values:
" PECI0 Temperature, 0x33
" PECI1 Temperature, 0x1A
" PECI2 Temperature, 0x1B
" PECI3 Temperature, 0x1C
These are the relative temperature values returned by the
CPU. If a CPU is not populated then its associated
temperature register can be written to by an external master.
Data is tored in 2s complement format.
PECI Absolute Temperature Values:
" PECI0_Abs Temperature, 0x04
" PECI1_Abs Temperature, 0x05
" PECI2_Abs Temperature, 0x06
" PECI3_Abs Temperature, 0x07
These are the absolute CPU temperature values. They are
automatically calculated by the NCT7491 from the relative
temperature and the CPU T
JMAX
value. See the PECI
T
JMAX
Values section. Data is stored in unsigned format.
Absolute PECI mode
The user can enable Absolute PECI mode by setting bit 2
of register 0x73 (ABS/REL) which will use the value stored
in the PECI absolute temperature registers for fan control,
THERM behaviour and SMBALERT behaviour rather than
the relative PECI values.
PECI Averaging
The number of samples over which the PECI master will
calculate an averaged temperature reading for each CPU can
be set in register 0x36, bits <2:0>:
" <000> = No averaging
" <001> = Averaged over 2 samples
" <010> = Averaged over 4 samples
" <011> = Averaged over 8 samples
" <100> to <111> are reserved
PECI Offsets:
" PECI0 Offset, 0x94
" PECI1 Offset, 0x95
" PECI2 Offset, 0x96
" PECI3 Offset, 0x97
Offset values can be assigned to each temperature channel
by programming these registers. The value programmed
should be in 2s complement format. The resolution is 1癈.
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