參數(shù)資料
型號(hào)： NCT7491RQR2G
廠商： ON Semiconductor
文件頁(yè)數(shù)： 53/80頁(yè)
文件大?。?/td> 844K
描述： IC REMOTE THERMAL MONITOR 24QSOP
標(biāo)準(zhǔn)包裝： 2,500
系列： *
NCT7491
http://onsemi.com
53
Table 64. REGISTER 0x40  Configuration Register 1 (PowerOn Default = 0x84)
Bit
Name
R/W
Description
<0>
STRT
(Notes 18, 19)
R/W
Logic 1 enables monitoring and PWM control outputs based on the limit settings programmed.
Logic 0 disables monitoring and PWM control is based on the default powerup limit settings.
Note that the limit values programmed are preserved even if a Logic 0 is written to this bit and
the default settings are enabled. This bit does not become locked once Bit 1 (LOCK bit) has
been set.
<1>
LOCK
Write once
Logic 1 locks all limit values to their current settings. Once this bit is set, all lockable registers
become readonly and cannot be modified until the NCT7491 is powered down and powered
up again. This prevents rogue programs such as viruses from modifying critical system limit
settings. (Lockable.)
<2>
RDY
R
This bit is set to 1 by the NCT7491 to indicate that the device is fully poweredup and ready
to begin system monitoring.
<3>
Fan Boost
R/W
When this bit is set to logic 1 all PWM outputs go to 100% regardless of other fan speed
configurations and automatic fan speed control settings. When this bit is set to 0 the fan
speed control returns to the fan speed setting calculated by the preprogrammed fan speed
control settings. This bit remains writable after the lock bit is set.
<4>
PECI Monitor
R/W
Set this bit to logic 1 to enable CPU thermal monitoring via PECI interface. This bit becomes
read only when the lock bit is set.
<5>
THERM
Override
R/W
When this bit is set to logic 1, any THERM
 pin assertion will cause the fans to go to 100% or
Max PWM, depending on bits <4:2> of register 0x16, overriding any other fan setting, even
when the PWMs are configured for manual mode, or disabled. This bit becomes read only
when the lock bit is set.
<7:6>
AVELN
R/W
Sets the averaging length for all analog channels
00 = 4 readings per averaged value
01 = 8 readings per averaged value
10 = 16 readings per averaged value
11 = 32 readings per averaged value
18.Bit 0 (STRT) of Configuration Register 1 (0x40) remains writable after lock bit is set.
19.When monitoring (STRT) is disabled, PWM outputs always go to 100% for thermal protection.
Table 65. REGISTER 0x41  Interrupt Status Register 1 (PowerOn Default = 0x00)
Bit
Name
R/W
Description
<0>
2.5 V
R
2.5 V = 1 indicates that the 2.5 V high or low limit has been exceeded. This bit is cleared on a read of
the status register only if the error condition has subsided.
<1>
V
CCP
R
V
CCP
 = 1 indicates that the V
CCP
 high or low limit has been exceeded. This bit is cleared on a read of
the status register only if the error condition has subsided.
<2>
V
CC
R
V
CC
 = 1 indicates that the V
CC
 high or low limit has been exceeded. This bit is cleared on a read of
the status register only if the error condition has subsided.
<3>
5 V
R
A 1 indicates that the 5 V high or low limit has been exceeded. This bit is cleared on a read of the
status register only if the error condition has subsided.
<4>
RIT
R
RIT = 1 indicates that the Remote 1 low or high temperature has been exceeded. This bit is cleared
on a read of the status register only if the error condition has subsided.
<5>
LT
R
LT = 1 indicates that the local low or high temperature has been exceeded. This bit is cleared on a
read of the status register only if the error condition has subsided.
<6>
R2T
R
R2T = 1 indicates that the Remote 2 low or high temperature has been exceeded. This bit is cleared
on a read of the status register only if the error condition has subsided.
<7>
OOL
R
OOL = 1 indicates that an outoflimit event has been latched in Status Register 2. This bit is a logic-
al OR of all status bits in Status Register 2 (0x42). Software can test this bit in isolation to determine
whether any of the voltage, temperature, or fan speed readings represented by Status Register 2 are
outoflimit, which eliminates the need to read Status Register 2 during every interrupt or polling
cycle.
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