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參數(shù)資料
| 型號： | NCT7491RQR2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 16/80頁 |
| 文件大?。?/td> | 844K |
| 描述： | IC REMOTE THERMAL MONITOR 24QSOP |
| 標準包裝： | 2,500 |
| 系列： | * |
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NCT7491
http://onsemi.com
16
also write thermal data to the Package Configuration Space
in the CPU. A PECI reading is a negative value, in degrees
Celsius, which represents the offset from the thermal control
circuit (T
CC
) activation temperature. PECI information is
returned as a 16bit 2s complement value from which the
8bit 2s complement value is derived. See the Platform
Environment Control Interface (PECI) Specification from
Intel for more details on the PECI data format. The PECI
temperature stored for each CPU is an averaged value; the
averaging window is user programmable.
The NCT7491 automatically detects the presence of a
CPU at each of the supported addresses, and also detects the
number of supported domains for each CPU. The presence
of each CPU is indicated in the NCT7491 status registers.
On power up, the PECI interface will become active when
the voltage measured on VTT is above 0.5 V and the voltage
on Vccp is above 0.5 V. The returned CPU temperature will
determine the behavior of the fans on powerup.
Thermal data that is collected by the NCT7491 (e.g. the
DIMM temperatures) can be written to the CPUs Package
Configuration Space (PCS) over the PECI 3.0 interface.
This data can be used by the CPU to modify memory
operations based on the DIMM temperature.
There are associated high and low limits for each PECI
reading that can be programmed. The limit values take the
same format as the PECI reading. Therefore, the
programmed limits are not absolute temperatures but a
relative offset in degrees Celcius from the TCC activation
temperature. An outoflimit event is recorded as follows:
" High Limit > comparison performed
" Low Limit d comparison performed
An outoflimit event is recorded in the associated status
register and can be used to assert the SMBALERT pin.
A generic PECI 3.0 interface command structure is also
available to allow an external master to issue any PECI 3.0
command in addition to the commands implemented by the
NCT7491 monitoring loops.
PECI V
TT
Input
The PECI V
TT
voltage is used as the reference voltage for
the PECI interface. This voltage must be connected to the
NCT7491 in order for the PECI interface to be operational.
The PECI V
TT
input is also monitored by the NCT7491 and
has associated high and low limits to allow outoflimit
detection on the V
TT
channel. The valid operational voltage
range for PECI V
TT
is 0.85 V to 1.26 V.
PECI Startup Operation
On power up of the NCT7491 the PECI V
TT
pin and the
Vccp pin are monitored. If the voltage on both of these pins
rises above 0.5 V then the NCT7491 will wait 5 ms and then
automatically scan the PECI port to check for the presence
of PECI 3.0 enabled processors. For any processors that are
detected the PECI address, the domain count, the Tcontrol
value and the Tjmax value will be read and stored in the
NCT7491. The CPU count bits will be set (bits <7:6> of
register 0x88). The PDET bit (bit <0> 0f register 0x37) will
also be set to indicate that at least one CPU was detected. If
any processors are detected then the PECI monitoring loop
will automatically start.
The Vccp pin must be connected to an input voltage for the
PECI interface to function correctly. If it is not connected to
the CPU supply voltage then it should be connected to the
NCT7491 supply voltage, Vcc. If the system processor does
not support PECI 3.0 then the PECI monitoring loop will not
automatically start. In that case the user can write to the
PECI registers to manually configure the interface. The
register descriptions are given below.
PECI Error Detection
The PECI 3.0 protocol includes FCS (Frame Check
Sequence) bytes to guarantee data integrity. If there is a
mismatch between the data and the FCS then a status bit
indicates the communication failure (COMM status bit,
register 0x43 bit <2>). PECI 3.0 also supports processor
specific error codes to indicate error conditions relating to
the temperature sensor within the processor (DATA status
bit, register 0x43 bit <1>). These codes are shown in
Table 8:
Table 8. DATA ERROR CODES
DATA code bits
<6:4>, 0x43
DATA
Error code
Description
<000>
0x8000
General Sensor Error
<001>
0x8002
Temperature below
operational range
<010>
0x8003
Temperature above
operational range
PECI Completion Code
Each read or write operation to the CPU Package
Configuration Space returns a completion code to indicate
the success or failure of the operation. The completion codes
supported are shown in Table 9:
Table 9. COMPLETION CODES
Completion
Code
Description
0x40
Command Passed, data is valid
0x80
Command timed out. Processor cannot gener-
ate required response in a timely fashion.
Retry is appropriate.
0x81
Command timed out. Processor cannot alloc-
ate resources for the request. Retry is appro-
priate.
0x90
Unknown/Invalid/Illegal request
0x91
PECI Control hardware, firmware or associ-
ated logic error. The processor cannot process
the request.
The completion code status bit in the NCT7491 (register
0x81 bit <0>) indicates the result of each read/write
operation.
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