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參數(shù)資料
| 型號： | NCT7491RQR2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 34/80頁 |
| 文件大?。?/td> | 844K |
| 描述： | IC REMOTE THERMAL MONITOR 24QSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | * |
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NCT7491
http://onsemi.com
34
Figure 23. THERM Timer
THERM Timer Limit
The THERM Timer limit register can be used to assert an
SMBALERT output when the timer measurement exceeds
the programmed limit value. If the value N is programmed
to the limit register then the limit time will be (N + 1) x 22.76
ms.
SMBALERT Functions
All of the measured temperatures, voltages and fan speeds
have associated limit registers to detect when an out of limit
condition occurs on any channel. Each of these channels has
an associated status bit that can be read over the SMBus to
determine the limit. There are also status bits to indicate the
success or failure of various functions, such as the PECI
interface or the SMBus Master Port interface. If a pin is
configured as an SMBALERT pin then any of the status bits
can assert the pin when they are set by the NCT7491. Most
of the status bits can be masked, allowing the user to prevent
assertion of the SMBALERT pins by functions that are not
required in an application. Descriptions of the limit registers
for each temperature, voltage or fan channel are described
in their relevant sections of this document.
Enabling Pins as SMBALERT Pins
" Setting bit 0 of register 0x78 sets pin 10 on the QSOP
package, or pin 7 on the QFN package as an
SMBALERT pin.
" Setting bits <1:0> of register 0xD to <10> sets pin 14
on the QSOP package or pin 11 on the QFN package as
an SMBALERT pin.
" Setting bits <3:2> of register 0x7C to <00> sets pin 19
on the QSOP package or pin 16 on the QFN package as
an SMBALERT pin.
NCT7491 Status Bits
When a status bit is set and the SMBALERT output asserts
it may be necessary to read the status registers to determine
the source of the assertion. To minimize to number of
register reads required the NCT7491 uses Out Of Limit bits
(OOL bits) to indicate in which registers an assertion has
occurred.
By first reading Status OOL register address 0x12 it can
be determined which other status registers are active. Once
set, a status bit will remain set until the register that it is
contained in is read over the SMBus interface, even if the
fault that caused the assertion is no longer present.
OOL register 0x12 Definitions:
" Bit 0 of 0x12 = 1 indicates an assertion in register 0x41
(Analog temperature and Voltage limit errors)
" Bit 1 of 0x12 = 1 indicates an assertion in register 0x7E
(Push register limit errors)
" Bit 2 of 0x12 = 1 indicates an assertion in register 0xB6
(SMBus Master NACK errors)
" Bit 3 of 0x12 = 1 indicates an assertion in register 0xB7
(SMBus Master PEC errors)
" Bit 4 of 0x12 = 1 indicates an assertion in register 0xB8
(SMBus Master Timeout errors)
" Bit 5 of 0x12 = 1 indicates an assertion in register 0xB9
(SMBus Master limit errors)
" Bit 6 of 0x12 = 1 indicates an assertion in register
0xBA (SMBus Master Data Invalid errors)
" Bit 7 of 0x12 = 1 indicates an assertion in register 0x89
(Tcontrol/THERM assertions). This bit relates to
THERM function and does not affect the SMBALERT
pins.
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