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參數(shù)資料
| 型號： | NCT7491RQR2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 61/80頁 |
| 文件大?。?/td> | 844K |
| 描述： | IC REMOTE THERMAL MONITOR 24QSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | * |
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NCT7491
http://onsemi.com
61
Table 87. REGISTER 0x77 Extended Resolution Register 2 (Note 36) (PowerOn Default = 0x00)
Bit
Name
R/W
Description
<1:0>
12 V
R
12 V LSBs. Holds the 2 LSBs of the 10bit 12 V measurement.
<3:2>
TDM1
R
Remote 1 Temperature LSBs. Holds the 2 LSBs of the 10bit Remote 1 temperature measurement.
<5:4>
LTMP
R
Local Temperature LSBs. Holds the 2 LSBs of the 10bit local temperature measurement.
<7:6>
TDM2
R
Remote 2 Temperature LSBs. Holds the 2 LSBs of the 10bit Remote 2 temperature measurement.
36.If this register is read, this register and the registers holding the MSB of each reading are frozen until read.
Table 88. REGISTER 0x78 Configuration Register 3 (PowerOn Default = 0x00)
Bit
Name
R/W
(Note 37)
Description
<0>
ALERT
R/W
ALERT = 1, Pin 10 on the QSOP package, Pin 7 on the QFN package (PWM2/SMBALERT
) is
configured as an SMBALERT
interrupt output to indicate outoflimit error conditions.
ALERT = 0, Pin 10 on the QSOP package, Pin 7 on the QFN package (PWM2/SMBALERT
) is
configured as the PWM2 output.
<1>
THERM
/
2.5 V
R/W
THERM
= 1 enables THERM
functionality on Pin 22 on the QSOP package, Pin 19 on the QFN
package
<2>
Reserved
R
<3>
FAST
R/W
FAST = 1 enables fast TACH measurements on all channels. This increases the TACH measure-
ment rate from once per second to once every 250 ms (4 x).
<4>
DC1
R/W
DC1 = 1 enables TACH measurements to be continuously made on TACH1. Fans must be driven
by dc. Setting this bit prevents pulse stretching because it is not required for dcdriven motors.
<5>
DC2
R/W
DC2 = 1 enables TACH measurements to be continuously made on TACH2. Fans must be driven
by dc. Setting this bit prevents pulse stretching because it is not required for dcdriven motors.
<6>
DC3
R/W
DC3 = 1 enables TACH measurements to be continuously made on TACH3. Setting this bit pre-
vents pulse stretching because it is not required for dcdriven motors.
<7>
DC4
R/W
DC4 = 1 enables TACH measurements to be continuously made on TACH4. Setting this bit pre-
vents pulse stretching because it is not required for dcdriven motors.
37.Bits <3:0> of this register become readonly when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to bits <3:0>
have no effect.
Table 89. REGISTER 0x79 THERM
Timer Value Register (PowerOn Default = 0x00)
Bit
Name
R/W
Description
<7:1>
TMR
R
Times how long THERM
input is asserted. These seven bits read zero until the THERM
assertion time
exceeds 45.52 ms.
<0>
ASRT/
TMR0
R
This bit is set high on the assertion of the THERM
input and is cleared on read. If the THERM
asser-
tion time exceeds 45.52 ms, this bit is set and becomes the LSB of the 8bit TMR reading. This allows
THERM
assertion times from 45.52 ms to 5.82 sec to be reported back with a resolution of 22.76 ms.
Table 90. REGISTER 0x7A THERM
Timer Limit Register (PowerOn Default = 0xFF)
Bit
Name
R/W
Description
<7:0>
LIMT
R/W
Sets maximum THERM
assertion length allowed before an interrupt is generated. This is an
8bit limit with a resolution of 22.76 ms allowing THERM
assertion limits of 45.52 ms to 5.82 s
to be programmed. If the THERM
assertion time exceeds this limit, Bit 5 (F4P) of Interrupt
Status Register 2 (Reg. 0x42) is set. If the limit value is 0x00, an interrupt is generated immedi-
ately on the assertion of the THERM
input. If THERM
is configured as an output the THERM
timer limit should be set to 0xFF to avoid unwanted alerts from being generated.
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