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參數(shù)資料
| 型號： | NCT7491RQR2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 21/80頁 |
| 文件大?。?/td> | 844K |
| 描述： | IC REMOTE THERMAL MONITOR 24QSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | * |
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NCT7491
http://onsemi.com
21
These registers are used to set the allowable Thermal slave
temperature range. If the temperature is above the high limit
or below the low limit then a status bit is set and pins
configured as SMBALERT will assert. The high and low
limit values are common to all SMBus Thermal slave
readings. The low limit is programmed as a 2s Complement
value. The high limit is programmed as an unsigned value.
The difference between the two formats is necessary to cover
the alternate formats available for the SMBus slave devices.
Thermal Slave THERM Value:
" SMBus THERM Limit, 0xC3
This value sets the failsafe THERM assertion
temperature. The response of the fans is determined by the
THERM configuration registers and is described in the
THERM Assertion section of this document. This value is
programmed as an 8bit unsigned value.
Thermal Slave Fan Control:
" SMB Device Tmin, 0xC6
" SMB Device Trange, 0xC7 bits <3:0>
" PWM1 Source2, 0x8B
" PWM2 Source2, 0x8E
" PWM3 Source2, 0x91
Tmin sets the turnon temperature for any fan that is
controlled by a Thermal slave device. Trange sets the
temperature range over which the PWM output will increase
from PWMmin to PWMmax. The Tmin and Trange values
apply to all Thermal slave devices. SMB Tmin is
programmed as an 8bit unsigned value. The maximum
valid SMBus Tmin value is 175癈.
The PWMX Source registers are used to assign
temperature control to a fan.
For full details on the Fan Control implementation see the
Fan Control section of this document.
SMBus Master Communication Settings
" Repeated Start Enable, 0xB0 bits <7:0>
" PEC Supported, 0xB1 bits <7:0>
The Repeated Start bits enable/disable the repeated start
protocol for each device.
The PEC Supported bits can be set if an SMBus client
device supports CRC8 PEC. If this bit is set for a client
device then the NCT7491 will read the PEC byte after the
data and set the corresponding bit in the PEC status register
(0xB7) if the PEC byte is incorrect.
DIMM Temperatures from PCH
" Read DIMM from PCH, 0xB5 bit 7
If this bit is set to 1 then the SMBus master port will read
the DIMM registers from the SMLINK1 port of the PCH and
store the results in registers 0xA9 to 0xAC. If it is 0 then it
will read DIMM temperatures from SMBus slave devices.
DIMM Temperatures from Remote Sensors
" DIMM 0/1 from Remote1, 0xB5 bit 5
" DIMM 2/3 from Remote2, 0xB5 bit 6
If 0xB5 <5> is 1 then registers 0xA9 and 0xAA are
overwritten by the Remote1 temperature reading.
If 0xB5 <6> is 1 then registers 0xAB and 0xAC are
overwritten by the Remote2 temperature reading.
If bit 7 of 0xB5 (DIMM from PCH) is set then bits 5 and
6 have no effect.
Writing DIMM temperatures to the CPUs
The DIMM temperatures collected from SPD devices,
from the PCH or from the analog thermal sensors can be
automatically written to the CPU via PECI. To enable this
function set the PWEN bit, register 0x37 <7>. The
temperatures written will be the maximum DIMM
temperature for each CPU.
DIMM CPU assignments:
" DIMM0 CPU, 0x0F bits <1:0>
" DIMM1 CPU, 0x0F bits <3:2>
" DIMM2 CPU, 0x0F bits <5:4>
" DIMM3 CPU, 0x0F bits <7:6>
These bits set the CPU associated with each DIMM. This
information is necessary in order for the PECI loop to
program the maximum DIMM temperature for each CPU.
Selecting DIMMs To Be Written
Each DIMM register can be enabled to be written to the
CPU individually. This is done in register 0x87 bits <7:4>.
If a DIMM is not populated then the corresponding bit in this
register should be set to zero:
Setting 0x87 bit <4> to 1 includes DIMM0 in the PECI write
Setting 0x87 bit <5> to 1 includes DIMM1 in the PECI write
Setting 0x87 bit <6> to 1 includes DIMM2 in the PECI write
Setting 0x87 bit <7> to 1 includes DIMM3 in the PECI write
SMBus Thermal Slave Error Response
How the NCT7491 responds to errors on the SMBus
master port can be configured in the following ways:
" SMBus Retry Interval, 0x10 bits <4:3>
" PWM1 Response, 0x11 bit 5
" PWM2 Response, 0x11 bit 6
" PWM3 Response, 0x11 bit 7
SMBus Retry Interval: If an error is encountered when
communicating with a Thermal slave device then the
NCT7491 will attempt to carry out the command up to 3
times. These bits set the interval between the retry attempts.
Table 21. SMBUS ERROR RETRY TIMES
0x10 bits <4:3>
SMBus Retry Interval
00
1 ms
01
2 ms
10
4 ms
11
8 ms
If the device fails 3 consecutive read attempts then the
PWMx Response bits determine the fan behaviour.
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