參數(shù)資料
型號(hào)： NCT7491RQR2G
廠商： ON Semiconductor
文件頁數(shù)： 51/80頁
文件大?。?/td> 844K
描述： IC REMOTE THERMAL MONITOR 24QSOP
標(biāo)準(zhǔn)包裝： 2,500
系列： *
NCT7491
http://onsemi.com
51
Table 56. REGISTER 0x36 PECI CONFIGURATION REGISTER 1 (PowerOn Default = 0x00)
BIT
NAME
R/W
Description
<2:0>
AVG
R/W
PECI Averaging Count
Code
Averaged Samples
000
1
001
2
010
4
011
8
100
Reserved
101
Reserved
110
Reserved
111
Reserved
<3>
DOM0
R/W
CPU Domain Count information. Set to 0 indicates that CPU 1 associated with the PECI0 reading
has a single domain (Default). Set to 1 indicates that the system CPU 1 contains two domains.
<4>
Reserved
<5>
Reserved
<7:6>
Reserved
Table 57. REGISTER 0x37 PECI CONFIGURATION REGISTER 3 (PowerOn Default = 0x32)
Bit
Name
R/W
Description
<0>
PDET
R/W
1 = at least one PECI enabled processor detected
0 = no processors detected
<1>
RTYDIS
R/W
1 = PECI retry bit is disabled
0 = PECI retry bit is enabled
This bit allows the user to disable the PECI retry bit for any subsequent commands following a
bad Completion Code from the CPU. It is enabled by default.
<2>
Reserved
R
<3>
Reserved
R
<5:4>
Rate
R/W
PECI update rate
00 = 1/sec
01 = 2/sec
10 = 5/sec
11 = 10/sec
<6>
Reserved
<7>
PWEN
R/W
1=PECI CPU writes are enabled
0=PECI CPU writes are disabled
Table 58. MAXIMUM PWM DUTY CYCLE (PowerOn Default = 0xFF) (Note 16)
Register Address
R/W
2
Description
0x38
R/W
Maximum duty cycle for PWM1 output, default = 100% (0xFF.)
0x39
R/W
Maximum duty cycle for PWM2 output, default = 100% (0xFF).
0x3A
R/W
Maximum duty cycle for PWM3 output, default = 100% (0xFF).
16.These registers set the maximum PWM duty cycle of the PWM output.
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