參數(shù)資料
型號: MT90500
廠商: Mitel Networks Corporation
英文描述: Multi-Channel ATM AAL1 SAR
中文描述: 多通道自動柜員機AAL1特區(qū)
文件頁數(shù): 97/159頁
文件大?。?/td> 514K
代理商: MT90500
MT90500
97
Table 44 - Receive Data Cell FIFO Base Address Register
Address: 4020 (Hex)
Label: RXDFBA
Reset Value: 0000 (Hex)
Label
Bit Position
Type
Description
RXFFBASE
11:0
R/W
Receive Data Cell FIFO Base Address. Represents address bits <20:9> that point to the
first structure in the Receive Data Cell FIFO. The lower address bits <8:0> of the pointer
are “0_0000_0000”. Each cell occupies a 64-byte buffer. Bit<0> of this field must always
be ‘0’. The Receive Data Cell FIFO must not overlap an 8 Kbyte boundary. When this
register is changed, FFENA in the UTOPIA Control Register at 4000h must not be
asserted.
RXFFSIZ
13:12
R/W
Receive Data Cell FIFO Size. This field contains the number of non-CBR data cells in the
Receive Data Cell FIFO. “00”=16 cells; “01”=32 cells; “10”=64 cells; “11”=128 cells. When
this register is changed, FFENA in the UTOPIA Control Register at 4000h must not be
asserted.
Reserved
15:14
R/W
Reserved. Always read as “00”.
Table 45 - Receive Data Cell FIFO Write Pointer Register
Address: 4022 (Hex)
Label: RXDFWP
Reset Value: 0000 (Hex)
Label
Bit Position
Type
Description
RXFFWP
7:0
R/O
Receive Data Cell FIFO Write Pointer. Indicates cell structure number in which the
UTOPIA module is currently writing (the cell is not valid yet) within the Receive Data Cell
FIFO.
Reserved
15:8
R/O
Reserved. Always read as 00h.
Table 46 - Receive Data Cell FIFO Read Pointer Register
Address: 4024 (Hex)
Label: RXDFRP
Reset Value: 0000 (Hex)
Label
Bit Position
Type
Description
RXFFRP
7:0
R/W
Receive Data Cell FIFO Read Pointer. Indicates the cell structure number in which the
CPU is currently reading (the cell is still valid). Must be set by CPU as cells are read.
Reserved
15:8
R/O
Reserved. Always read as 00h.
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