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參數(shù)資料
| 型號(hào)： | MT90500 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Multi-Channel ATM AAL1 SAR |
| 中文描述： | 多通道自動(dòng)柜員機(jī)AAL1特區(qū) |
| 文件頁(yè)數(shù)： | 107/159頁(yè) |
| 文件大?。?/td> | 514K |
| 代理商： | MT90500 |
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MT90500
107
FREERUN
12:11
R/W
Clock Failure Detection - FREERUN Signal Control
00 -> FREERUN is always activated (FREERUN pin is HIGH)
01 -> FREERUN is activated when status bit REFFAIL (in the Clock Module General
Status Register at 6082h) is ‘1’. In the event of REF8KCLK clock failure, it is the software’s
responsibility to change the programming from “01” to “00” before clearing the REFFAIL
status bit.
1X -> FREERUN is always deactivated (FREERUN pin is LOW)
Reserved
15:13
R/W
Reserved. Should be written as “000”.
Refer to Figure 3, “TDM Clock Selection and Generation Logic,” on page 29 for more detailed information regarding the implementation of the
selection bits.
Table 62 - Master Clock / CLKx2 Division Factor
Address: 6092 (Hex)
Label: MCDF
Reset Value: 2000 (Hex)
Label
Bit Position
Type
Description
DIVCLK
13:0
R/W
This value plus two is used to divide MCLK or CLKx2 to get an 8 kHz reference. Value
0000h means divide-by-two, 0001h means divide-by-three, ..., 3FFEh means divide-by-
16,384.
Reserved
15:14
R/W
Reserved. Should be written as “00”.
Table 63 - Timing Reference Processing Control Register
Address: 60A0 (Hex)
Label: TRPCR
Reset Value: 0001 (Hex)
Label
Bit
Position
Type
Description
Time-out
9:0
R/W
This value is used to indicate a time-out period, after which if no timing reference cells or
markers have been received, a Loss of Timing Reference Cells (LOSS_TIMRF in 6082h)
event will be indicated. The time-out period is calculated in multiples of 65536 MCLK
periods. “00_0000_0000” is an illegal value (i.e. time-out is a minimum of 65536 cycles of
MCLK).
Cell / 8 kHz
10
R/W
When ‘0’, indicates that clock recovery is based on Timing Reference Cell arrival events.
When ‘1’, indicates that clock recovery is based on 8 kHz marker arrival events.
Seq_CRC_Ena
11
R/W
When ‘1’, enable CRC and parity checking on AAL1 sequence number field in state
machine. See Figure 31 on page 70.
Reserved
15:12
R/W
Reserved. Should be written as “0000”.
Table 61 - Master Clock Generation Control Register
Address: 6090 (Hex)
Label: MCGCR
Reset Value: 00C0 (Hex)
Label
Bit Position
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90500AL | Multi-Channel ATM AAL1 SAR |
| MT90502 | Multi-Channel AAL2 SAR(多通道 ATM AAL2分段及重組設(shè)備（基于通訊總線的系統(tǒng)與ATM網(wǎng)絡(luò)的接口）) |
| MT90732AP | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90732 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90733 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90500AL | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Multi-Channel ATM AAL1 SAR |
| MT90500AL-ENG1 | 制造商:Mitel Networks Corporation 功能描述: |
| MT90502 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502_06 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502AG | 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
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