
MT90500
92
Table 27 - RX_SAR Status Register
Address: 3002 (Hex)
Label: RXSSR
Reset Value: 0000 (Hex)
Label
Bit
Position
Type
Description
Reserved
4:0
R/O
Reserved. Always read as “0_0000”.
APE
5
R/O/L
AAL1-byte Parity Error. ‘0’ = Event has not occurred. ‘1’ = Event has occurred. Writing a ‘1’
over this bit clears it.
ACE
6
R/O/L
AAL1-byte CRC Error. ‘0’ = Event has not occurred. ‘1’ = Event has occurred. Writing a ‘1’
over this bit clears it.
SNE
7
R/O/L
AAL1-byte Sequence Number Error. ‘0’ = Event has not occurred. ‘1’ = Event has occurred.
Writing a ‘1’ over this bit clears it.
PPE
8
R/O/L
Pointer-byte Parity Error. ‘0’ = Event has not occurred. ‘1’ = Event has occurred. Writing a
‘1’ over this bit clears it.
PORE
9
R/O/L
Pointer-byte Out of Range Error. ‘0’ = Event has not occurred. ‘1’ = Event has occurred.
Writing a ‘1’ over this bit clears it.
WURE
10
R/O/L
Write Underrun Error. ‘0’ = Event has not occurred. ‘1’ = Event has occurred. Writing a ‘1’
over this bit clears it.
WORE
11
R/O/L
Write Overrun Error. ‘0’ = Event has not occurred. ‘1’ = Event has occurred. Writing a ‘1’
over this bit clears it.
MCR
12
R/O/L
Misc. Counter Rollover. If set, the RX_SAR Misc. Event Counter Register at 3012h has
rolled over. Writing a ‘1’ over this bit clears it.
WURCR
13
R/O/L
Write Underrun Counter Rollover. If set, the RX_SAR Underrun Event Counter Register at
3022h has rolled over. Writing a ‘1’ over this bit clears it.
WORCR
14
R/O/L
Write Overrun Counter Rollover. If set, the RX_SAR Overrun Event Counter Register at
3032h has rolled over. Writing a ‘1’ over this bit clears it.
RXSERV
15
R/O/L
RX Service. This bit is set if any of bits<14:5> in this register is set. Writing a ‘1’ over this bit
clears it.
Table 28 - RX_SAR Misc. Event ID Register
Address: 3010 (Hex)
Label: RXMEID
Reset Value: 0000 (Hex)
Label
Bit
Position
Type
Description
MISCID
15:0
R/W
MISC. Event ID number. This 16-bit register holds bits<19:4> of the address of the RX
Control Structure that caused the last miscellaneous error. This register is only affected by
the miscellaneous errors that are selected via the 5 least significant bits of the RX_SAR
Control Register (3000h). This register will also be updated if the TESTS bit is set in the
RX_SAR Control Register.
Table 29 - RX_SAR Misc. Event Counter Register
Address: 3012 (Hex)
Label: RXMECT
Reset Value: 0000 (Hex)
Label
Bit
Position
Type
Description
MISCC
15:0
R/W
MISC. Event Count. This 16-bit register’s value is incremented each time a miscellaneous
error occurs. A miscellaneous error is considered to have occurred if any of bits<9:5> in the
RX_SAR Status Register at 3002h is set and the corresponding miscellaneous select bit in
bits<4:0> of the RX_SAR Control Register (3000h) is also set. This register is also
incremented if TESTS is set in the RX_SAR Control Register.