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參數(shù)資料
| 型號(hào)： | MT90500 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Multi-Channel ATM AAL1 SAR |
| 中文描述： | 多通道自動(dòng)柜員機(jī)AAL1特區(qū) |
| 文件頁(yè)數(shù)： | 63/159頁(yè) |
| 文件大小： | 514K |
| 代理商： | MT90500 |
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MT90500
63
.
4.5.2
Cell Transmission and Mux Process
The general block diagram of the Mux and internal FIFO sub-module is shown above. The Mux sub-module’s
operation is relatively straight-forward. It multiplexes onto the Primary Transmit UTOPIA Port cells generated by
the TX_SAR with cells received from the optional external SAR device. A number of register bits found at
address 4000h control the operation of the sub-module: a general enable (RXENA); an external SAR interface
enable (STXENA); and a mux arbitration method (RRP, which gives priority to the TX_SAR or allocates priority
in round-robin fashion).
4.5.3
Receive Cell Selection Process
The purpose of the Receive Cell Selection Process is to determine the routing of received ATM cells, which can
include OAM cells, timing reference cells, CBR cells destined for the RX_SAR, and non-CBR data cells which
will be routed to the Receive Data Cell FIFO. The steps involved in the Receive Cell Selection Process are
detailed below and are outlined in the flow chart in Figure 26.
The Receive Cell Selection Process is as follows:
a) The most significant bit of the PTI field in the cell header is examined to determine if the cell is an OAM cell.
If the received cell is an OAM cell, it is either sent to the 32-cell (2048-byte) internal Primary Receive FIFO, or
discarded as determined by the OAM Routing Select bit, OAMSEL, in the UTOPIA Control Register at 4000h.
OAM cells that are sent to this internal FIFO are then treated as non-CBR data cells and are eventually sent to
the Receive Data Cell FIFO in external memory; see step (e). If the cell is not an OAM cell, step (b) is taken.
b) Non-OAM cells are then passed through the MT90500’s timing filter mechanism. The VPI and VCI values of
the incoming cell are compared to the values found within the VPI Timing Register (401Ah) and the VCI Timing
Register (401Ch). If the VC of the received cell matches the Timing Registers, a timing pulse is sent to the
Clock Recovery Module, along with the AAL1 byte of the cell header (this process is explained in detail in
Section 4.6.1, “Adaptive Clock Recovery Sub-Module”). Regardless of whether the cell matches the timing filter
or not, the cell is sent to step (c) for further processing.
FIFO
TX MUX
RX FIFO & VC
Search Engine
DEVICE BOUNDARY
FIFO
FIFO
From
TX_SAR
To/From
Microprocessor I/F
To / From
TDM Module
Figure 25 - Mux and Internal FIFO Sub-Module Block Diagram
To/From
Memory Controller
To
RX_SAR
SECONDARY
UTOPIA PORT
PRIMARY
UTOPIA PORT
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90500AL | Multi-Channel ATM AAL1 SAR |
| MT90502 | Multi-Channel AAL2 SAR(多通道 ATM AAL2分段及重組設(shè)備（基于通訊總線的系統(tǒng)與ATM網(wǎng)絡(luò)的接口）) |
| MT90732AP | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90732 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90733 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90500AL | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Multi-Channel ATM AAL1 SAR |
| MT90500AL-ENG1 | 制造商:Mitel Networks Corporation 功能描述: |
| MT90502 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502_06 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502AG | 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
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