參數(shù)資料
型號： MT90500
廠商： Mitel Networks Corporation
英文描述： Multi-Channel ATM AAL1 SAR
中文描述： 多通道自動柜員機AAL1特區(qū)
文件頁數(shù)： 72/159頁
文件大?。?/td> 514K
代理商： MT90500
MT90500
72
The adaptive clock recovery method operates on a single receive VC which is defined by the VCI Timing
Register and the VPI Timing Register. The clock recovery method is, briefly, as follows:
Every (CLKx1 * 8) clock period, counter 1 (CLKx1 Counter) is incremented.
Every time an 8 kHz marker or a cell with the Timing Recovery ID is received, counter 2 (Event Counter)
is incremented. As well, the CLKx1 Counter value is latched to the Temp Register.
Periodically, the processor writes the CNTUPDATE bit in Clock Module General Control Register
(6080h) and reads both counters to determine if the local clock needs to be sped up or slowed down
with respect to the remote clock.
The local clock (RXVCLK) frequency is then adjusted by controlling the contents of the DIVX (60A8h)
and DIVX Ratio (60AAh) Registers.
Please refer to the MT90500 Programmers’ Manual for an example of an Adaptive Clock Recovery algorithm.
4.6.2
SRTS Clock Recovery Description
The Synchronous Residual Time Stamp (SRTS) method of clock recovery is standardized in ITU-T I.363.1 and
ANSI T1.630. This section outlines the operation of the MT90500 during transmit SRTS generation and receive
SRTS clock recovery. Note that SRTS may be used in different applications than Adaptive Clock Recovery
because SRTS produces a clock which better meets public network specifications for jitter and wander, but
requires a common (synchronous) ATM physical layer reference clock at both ends. Please refer to MSAN-171
- “TDM Clock Recovery from CBR-over-ATM Links Using the MT90500” for applications of Synchronous
Residual Time Stamp clocking.
Please note that Mitel has entered into an agreement with Bellcore with respect to
Bellcore’s U.S. Patent No. 5,260,978 and Mitel’s manufacture and sale of products
containing the SRTS function. However the purchase of this product does not grant
the purchaser any rights under U.S. Patent No. 5,260,978. Use of this product or its re-
sale as a component of another product may require a license under the patent which
is available from Bell Communications Research, Inc., 445 South Street, Morristown,
New Jersey 07960.
Since all of the TDM data streams on the MT90500 serial bus are synchronized to a single clock and frame
pulse, the SRTS clock recovery module generates a single clock, from a single source VC. Although the
MT90500 may receive several CBR VCs from various sources, the serial bus clocks can be locked only to one
of the incoming VCs. Similarly, only one specific VC is selected to transmit the SRTS information from the
MT90500 device. The ‘AS’ (AAL Type) fields within the Transmit Control Structure (see Figure 16) and the
RX_SAR Control Structure (refer to Figure 22) are used to designate the particular transmit and receive VCs
that will carry the SRTS information. Note that only AAL1-type cells can be used to transmit SRTS data as the
CSI bit in the AAL1 header byte is used to carry the information.
4.6.2.1
Transmit SRTS Operation
In the transmit SRTS operation, the MT90500 compares the local service clock (derived from CLKx1) to a
divided-down version of the network clock (available at the FNXI input pin). The SRTS method uses a stream of
residual time stamps (RTS) to communicate the difference between a common reference clock (f
nx
, derived
from the network) and a local service clock (f
S
, derived from the local TDM clock). If the same ATM physical
layer reference clock is available at both the origin and destination points (e.g. two different MT90500s), the
service clock can be recovered at the destination using the common reference clock, the transmitted (remote)
RTS, and a locally-generated RTS.
Within the MT90500 SRTS module, the RTS service clock is derived from the TDM clock signals. The CLKx1
main TDM bus clock is used to obtain a clock, f
B
, which represents the TDM byte frequency of the SRTS
transmit VC. f
B
is equal to N * 8 kHz, where N is the number of TDM input channels in the VC which is selected
for SRTS transmission (f
B
is one-eighth of the service clock, f
s
). To generate f
B
, N pulses are spaced more or
less evenly within the 125
μ
s period defined by the input signal FSYNC. The number of pulses per period and
their spacing are determined by the settings within the SRTS Transmit Gapping Divider Register at address
60B0h. For instance, if there are 64 channels in the SRTS VC, N = 64, and the resulting byte rate, f
B
, is 512
kHz (T
B
= 125
μ
s / 64). In order to implement this configuration, the register at 60B0h should be set as follows:
TX_Ch_per_VC = 3Fh while the TX_Gapping field is set to 3h. (Please refer to “SRTS Transmit Gapping
Divider Register,” on page 109 for configuration details.)
相關(guān)PDF資料
PDF描述
MT90500AL Multi-Channel ATM AAL1 SAR
MT90502 Multi-Channel AAL2 SAR(多通道 ATM AAL2分段及重組設備（基于通訊總線的系統(tǒng)與ATM網(wǎng)絡的接口）)
MT90732AP Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
MT90732 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
MT90733 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT90500AL 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Multi-Channel ATM AAL1 SAR
MT90500AL-ENG1 制造商:Mitel Networks Corporation 功能描述:
MT90502 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR
MT90502_06 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR
MT90502AG 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述:
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*