- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383644 > MT90500 (Mitel Networks Corporation) Multi-Channel ATM AAL1 SAR PDF資料下載
參數(shù)資料
| 型號： | MT90500 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Multi-Channel ATM AAL1 SAR |
| 中文描述： | 多通道自動柜員機(jī)AAL1特區(qū) |
| 文件頁數(shù)： | 94/159頁 |
| 文件大?。?/td> | 514K |
| 代理商： | MT90500 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁當(dāng)前第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁
MT90500
94
5.2.4
UTOPIA Registers
Table 34 - UTOPIA Control Register
Address: 4000 (Hex)
Label: UCR
Reset Value: 0000 (Hex)
Label
Bit
Position
Type
Description
RXENA
0
R/W
RX Cell Enable. When ‘0’, all received cells are ignored. When ‘1’, received cells are
processed normally.
STXENA
1
R/W
Secondary TX Cell Enable. When this bit is ‘0’, no cells may be received from the
secondary TX interface. When ‘1’, the UTOPIA module receives cells from the secondary
SAR normally.
RRP
2
R/W
Round-Robin Priority. When ‘0’, CBR traffic from the MT90500 has priority over traffic from
the secondary SAR interface. When ‘1’, both traffic types have the same priority.
RXFFENA
3
R/W
Receive FIFO Enable. When this bit is LOW, the Receive Data Cell FIFO Write Pointer
(RXFFWP at 4022h) is reset to 00h. When this bit is HIGH, the FIFO can operate normally.
RXFFWP+
4
R/W
Increment Receive Data Cell FIFO Write Pointer. When ‘1’ is written on this bit, the
Receive Data Cell FIFO Write Pointer (RXFFWP at 4022h) is incremented. Used for test
purposes only.
OAMSEL
5
R/W
OAM Routing Select. ‘0’ = discard; ‘1’= treat as non-CBR data cell.
UKSEL
6
R/W
Unknown Routing Select. ‘0’ = discard cells with undefined entry types (i.e. T bits = “00” in
look-up table); ‘1’= treat cells with undefined entry types (i.e. T bits = “00” in look-up table)
as non-CBR data cells.
RXBASE
9:7
R/W
RX Control Structure Base Address. These three bits represent the three most significant
address bits<20:18> of the pointer to the Receive Control Structures.
RXFFORIE
10
R/W
Receive Data Cell FIFO Overrun Error Interrupt Enable. ‘0’ = Disabled; ‘1’ = Enabled.
When enabled, a ‘1’ on RXFFOR in Register 4002h will force a ‘1’ on MUX_SERV in
Register 0002h.
RXORIE
11
R/W
RX UTOPIA Module Internal FIFO Overrun Interrupt Enable. ‘0’ = Disabled; ‘1’ = Enabled.
When enabled, a ‘1’ on RXOR in Register 4002h will force a ‘1’ on MUX_SERV in Register
0002h.
RXFFRCIE
12
R/W
Receive Data FIFO Receive Cell Interrupt Enable. ‘0’ = Disabled; ‘1’ = Enabled. When
enabled, a ‘1’ on RXFFRC in Register 4002h will force a ‘1’ on MUX_SERV in Register
0002h.
Reserved
14:13
R/W
Reserved. Should be written as “00”.
TESTS
15
R/W
TEST Status. When HIGH, this bit forces the three status events (bits<12:10>) in the
UTOPIA Status Register at 4002h to occur. Used for test purposes only.
Table 35 - UTOPIA Status Register
Address: 4002 (Hex)
Label: USR
Reset Value: 0000 (Hex)
Label
Bit
Position
Type
Description
Reserved
9:0
R/O
Reserved. Always read as “00_0000_0000”.
RXFFOR
10
R/O/L
Receive Data Cell FIFO Overrun Error. When this bit is ‘1’, the RXFFWP (register 4022h) =
RXFFRP (register 4024h) and one or more non-CBR data cells were discarded because
the Receive Data Cell FIFO was full. Writing a ‘1’ over this bit clears it.
RXOR
11
R/O/L
Receive UTOPIA Module Internal FIFO Overrun. At least one CBR cell was lost because
the RX_SAR did not process the cells fast enough. Writing a ‘1’ over this bit clears it.
RXFFRC
12
R/O/L
Data FIFO Receive Cell. Each time a non-CBR data cell is received, this bit is set. Writing
a ‘1’ over this bit clears it.
Reserved
14:13
R/O
Reserved. Always read as “00”.
UTOSERV
15
R/O
UTOPIA Service. When any of the status bits in this register are HIGH, this bit is HIGH.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90500AL | Multi-Channel ATM AAL1 SAR |
| MT90502 | Multi-Channel AAL2 SAR(多通道 ATM AAL2分段及重組設(shè)備（基于通訊總線的系統(tǒng)與ATM網(wǎng)絡(luò)的接口）) |
| MT90732AP | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90732 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90733 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90500AL | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Multi-Channel ATM AAL1 SAR |
| MT90500AL-ENG1 | 制造商:Mitel Networks Corporation 功能描述: |
| MT90502 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502_06 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502AG | 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。