
MT90500
34
4.1.3.2
Transmit Circular Buffer Control Structures
To minimize the amount of external memory required for the TDM Data to External Memory Process, only the
TDM channels assigned to be transmitted over the ATM link are transferred to external memory. Each TDM
channel to be transmitted over the ATM link occupies a 64-byte Transmit Circular Buffer in external memory. As
shown in Figure 5, the MT90500 fetches control data from the Transmit Circular Buffer Control Structure in
external memory in order to determine which TDM channels to transfer to external memory and where to put
the data. The Transmit Circular Buffer Control Structure is a sequential control table consisting of 16-bit entries:
Bit<15> indicates that the entry is valid (active HIGH).
Bits<14:11> are not used, and should be set to zeroes.
Bits<10:0> identify a channel number.
Bits<10:4> identify a TDM channel within a stream. The channels are numbered from 0 to 127.
Bits<3:0> identify a stream number, from 0 to 15.
The first entry in the Transmit Circular Buffer Control Structure tells the hardware from which TDM channel it
will fill the first 64-byte Transmit Circular Buffer, the second entry tells the hardware from which TDM channel it
will fill the second Transmit Circular Buffer, and so on. If the entry is not valid (i.e. the V bit is not asserted), the
transfer is not executed. In order to prevent unnecessary transfer of TDM data to external memory, the user
should zero-out all unused entries within the TX Circular Buffer Control Structure.
0
4
15
12
21
V
TXCBCSBASE
TXCBCSL
Time Slot
V
V
V
V
V
+000
+002
+004
+006
Maximum of 2048
entries
TXCBCS
TDM Channels Control Data
Minimum of 128 entries (i.e.
words)
V = Entry Valid (bit<15>)
R = Reserved (bits<14:11> - set to all zeroes)
Time Slot = 7-bit TDM time slot select (bits<10:4>)
Stream = 4-bit TDM stream select (bits<3:0>)
R R
R R
R R
Stream
Time Slot
Stream
Time Slot
Stream
Time Slot
Stream
Time Slot
Stream
Time Slot
Stream
+FFE
3
<8:0>
<20:9>
6040h
<20:0>
Pointer to Start of
TX Circular Buffer
Control Structure
R
R
R
9
4
0
10
15
R
R
R
B “0_0000_0000”
Figure 5 - Transmit Circular Buffer Control Structure
Internal Memory
External Memory
R R
R R
R R
R R
R R
R R