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參數(shù)資料
| 型號： | MT90500 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Multi-Channel ATM AAL1 SAR |
| 中文描述： | 多通道自動柜員機AAL1特區(qū) |
| 文件頁數(shù)： | 113/159頁 |
| 文件大?。?/td> | 514K |
| 代理商： | MT90500 |
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MT90500
113
Precautions During Power Sequencing
Latch-up is not a concern during power sequencing. There is no requirement for sequencing 3.3 V and 5 V
supplies during power up. However, to minimize over-voltage stress during system start-up, the 3.3 V supply
applied to the MT90500 should be brought to a level of at least VDD = 3.0 V before a signal line is driven to a
level greater than or equal to 3.3 V. This practice can be implemented either by ensuring that the 3.3 V power
turns on simultaneously with or before the system 5 V supply turns on, or by ensuring that all 5 V signals are
held to a logic LOW state during the time that VDD < 3.0 V. Regardless of the method chosen to limit over-
voltage stress during power up, exposure must be limited to no more than + 6.5 V input voltage (V
IN
). The
TRISTATE pin of the MT90500 can be asserted low on power-up to prevent bus contention.
Precautions During Power Failure
Latch-up is not a concern in power failure mode. Although extended exposure of the MT90500 to 5 V signals
during 3.3 V supply power failure is not recommended, there are no restrictions as long as V
IN
does not exceed
the absolute maximum rating of 6.5 V. To minimize over-voltage stress during a 3.3 V power supply failure, the
designer should either link the power supplies to prevent this condition or ensure that all 5 V signals connected
to the MT90500 are held in a logic LOW state until the 5 V supply is deactivated.
Pull-ups
Pull-ups from the 5V rail to 3.3V (5V tolerant) outputs of the MT90500 can cause reverse leakage currents into
those 3.3V outputs when they are active HIGH. (No significant reverse current is present during the high
impedance state.) If the application can put the MT90500 in a state where MCLK is stopped, and a large
number of 3.3V output buffers are held in a static HIGH state, current can flow from the 5V rail to the 3.3V rail.
If this MCLK-stopped state can not be avoided, the user should determine if the total MT90500 reverse current
will have a negative impact on the system 3.3V power supply. Alternatively, the TRISTATE pin of the MT90500
can be asserted low to put all outputs in the high impedance state.
a. Typical figures are at 25
°
C and are for design aid only; not guaranteed and not subject to production testing.
b. T
OP
= -40
°
C to 85
°
C; V
DD5
= 5V
±
5%; V
DD3
= 3.3V
±
5%
Voltage measurements are with respect to ground (V
SS
) unless otherwise stated.
13
Differential Input Low Voltage
V
ILD
- 0.5
V
CLKx2PI - CLKx2NI
14
Input Leakage Current
Inputs with pull-down resistors
Inputs with pull-up resistors
I
IL
/ I
IH
±
1
±
10
μ
A
V
IN
= V
DDx
or V
ss
I
IH
69
124
190
μ
A
V
IN
= V
DD5
I
IL
- 70
- 142
- 225
μ
A
V
IN
= V
ss
15
Input Pin Capacitance
C
I
10
pF
16
Output HIGH Voltage
V
OH
2.4
3.3
V
DDX
V
I
OH =
rated current (4 or 12
mA)
17
Output LOW Voltage
V
OL
0.2
0.4
V
I
OL =
rated current (4 or 12
mA)
18
High Impedance Leakage
I
OZ
-10
±
1.0
+10
μ
A
V
O
= V
SS
or V
DD
19
Output Pin Capacitance
C
O
10
pF
Table 76 - DC Characteristics
Characteristics
Sym
Min
Typ
a
Max
Units
Test Conditions
b
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90500AL | Multi-Channel ATM AAL1 SAR |
| MT90502 | Multi-Channel AAL2 SAR(多通道 ATM AAL2分段及重組設(shè)備（基于通訊總線的系統(tǒng)與ATM網(wǎng)絡(luò)的接口）) |
| MT90732AP | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90732 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90733 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90500AL | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Multi-Channel ATM AAL1 SAR |
| MT90500AL-ENG1 | 制造商:Mitel Networks Corporation 功能描述: |
| MT90502 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502_06 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502AG | 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
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