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參數(shù)資料
| 型號(hào)： | MT90500 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Multi-Channel ATM AAL1 SAR |
| 中文描述： | 多通道自動(dòng)柜員機(jī)AAL1特區(qū) |
| 文件頁(yè)數(shù)： | 147/159頁(yè) |
| 文件大?。?/td> | 514K |
| 代理商： | MT90500 |
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MT90500
147
7.4
External Memory Space and Bandwidth Calculations
7.4.1
External Memory Space Requirements
This section provides a list of the control and data structures used by the MT90500 which are located in
external memory. An estimation of the structure size is provided, assuming various scenarios: 256, 512, and
1024 TDM channels in both directions and from 16 to 1024 VCs. (In line with accepted usage for memory, here
1 Kbyte = 1024 bytes.)
Transmit Memory Requirements
Refer to Figure 19, “Overview of CBR Data Transmission Process,” on page 54.
A. TX Circular Buffer Control Structure
Two bytes of RAM are required for every TDM channel transmitted.
256 TDM channels
512 TDM channels
1024 TDM channels
0.5 Kbyte
1 Kbyte
2 Kbytes
B. Transmit Circular Buffers
64 bytes of RAM are required for every TDM channel transmitted.
256 TDM channels
512 TDM channels
1024 TDM channels
16 Kbytes
32 Kbytes
64 Kbytes
C. Transmit Event Scheduler
Assume either 1 scheduler, or all 3 schedulers in service. Assume the schedulers are composed of 47 frames
(AAL1-SDT) and each frame contains 16 two-byte VC Pointer entries.
1 scheduler
3 schedulers
~ 1.5 Kbytes
~ 4.4 Kbytes
D. Transmit Control Structure
Each control structure begins with 12 bytes of control data, followed by 2 bytes of information for each TDM
channel. All transmit control structures occupy an integer number of 16-byte blocks.
16 VCs (16 TDM channels per VC)
128 VCs (4 TDM channels per VC)
1024 VCs (1 TDM channel per VC)
0.75 Kbyte (16 * ROUNDUP(12 + 16 * 2) = 768 bytes)
4 Kbytes (128 * ROUNDUP(12 + 4 * 2) = 4096 bytes)
16 Kbytes (1024 * ROUNDUP(12 + 1 * 2) = 16384 bytes)
E. Transmit Data Cell FIFO holding 64 cells
(Refer to Section 4.3.3.)
64 data cell structures at 64 bytes each
4 Kbytes
Sub-total external memory space requirements to support the TDM to ATM transmit process:
Minimum requirements (256 channels, 1 scheduler):
22.7 Kbytes
Maximum requirements (1024 channels, 3 schedulers):
90.4 Kbytes
Receive Memory Requirements
See Figure 30, “Overview of CBR Data Reception Process,” on page 69.
A. VC Look-up Table
Note: These numbers assume one-to-one mapping of look-up table entries to VCs. Larger “sparse” tables may
be used in some applications, up to 128 Kbytes.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90500AL | Multi-Channel ATM AAL1 SAR |
| MT90502 | Multi-Channel AAL2 SAR(多通道 ATM AAL2分段及重組設(shè)備（基于通訊總線的系統(tǒng)與ATM網(wǎng)絡(luò)的接口）) |
| MT90732AP | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90732 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90733 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90500AL | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Multi-Channel ATM AAL1 SAR |
| MT90500AL-ENG1 | 制造商:Mitel Networks Corporation 功能描述: |
| MT90502 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502_06 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502AG | 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
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