參數(shù)資料
型號(hào)： MPC5125YVN400
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 83/94頁(yè)
文件大?。?/td> 0K
描述： IC MCU 32BIT E300 324TEPBGA
標(biāo)準(zhǔn)包裝： 60
系列： MPC51xx
核心處理器： e300
芯體尺寸： 32-位
速度： 400MHz
連通性： CAN，EBI/EMI，以太網(wǎng)，I²C，USB OTG
外圍設(shè)備： DMA，WDT
輸入/輸出數(shù)： 64
程序存儲(chǔ)器類型： ROMless
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 1.08 V ~ 3.6 V
振蕩器型： 外部
工作溫度： -40°C ~ 125°C
封裝/外殼： 324-BBGA
包裝： 托盤
MPC5125 Microcontroller Data Sheet, Rev. 4
System Design Information
Freescale Semiconductor
84
5.4
Pullup/Pulldown Resistor Requirements
The MPC5125 requires external pullup or pulldown resistors on certain pins.
5.4.1
Pulldown Resistor Requirements for TEST Pin
The MPC5125 requires a pulldown resistor on the test pin TEST.
5.5
JTAG
The MPC5125 has an IEEE 1149.1 JTAG interface to facilitate board/system testing. It also provides a common on-chip
processor (COP) interface, which shares the IEEE 1149.1 JTAG port.
The COP interface provides access to the MPC5125’s embedded e300 processor and to other on-chip resources. This interface
provides a means for executing test routines and for performing software development and debug functions.
5.5.1
JTAG_TRST
Boundary scan testing is enabled through the JTAG interface signals. The JTAG_TRST signal is optional in the IEEE 1149.1
specification but is provided on all processors that implement the Power Architecture. To obtain a reliable power-on reset
performance, the JTAG_TRST signal must be asserted during power-on reset.
5.5.1.1
TRST and PORESET
The JTAG interface can control the direction of the MPC5125 I/O pads via the boundary scan chain. The JTAG module must
be reset before the MPC5125 comes out of power-on reset; do this by asserting TRST before PORESET is released.
For more details, see the Reset and JTAG Timing Specification.
Figure 50. PORESET vs. TRST
5.5.2
e300 COP/BDM Interface
There are two possibilities to connect the JTAG interface: using it with a COP connector and without a COP connector.
5.5.2.1
Boards Interfacing the JTAG Port via a COP Connector
The MPC5125 functional pin interface and internal logic provides access to the embedded e300 processor core through the
Freescale standard COP/BDM interface. Table 49 gives the COP/BDM interface signals. The pin order shown reflects only the
COP/BDM connector order.
TRST
PORESET
Required assertion of TRST
Optional assertion of TRST
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