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參數(shù)資料
| 型號： | MPC5125YVN400 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 43/94頁 |
| 文件大小： | 0K |
| 描述： | IC MCU 32BIT E300 324TEPBGA |
| 標準包裝： | 60 |
| 系列： | MPC51xx |
| 核心處理器： | e300 |
| 芯體尺寸： | 32-位 |
| 速度： | 400MHz |
| 連通性： | CAN，EBI/EMI，以太網(wǎng)，I²C，USB OTG |
| 外圍設(shè)備： | DMA，WDT |
| 輸入/輸出數(shù)： | 64 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 32K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.08 V ~ 3.6 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 324-BBGA |
| 包裝： | 托盤 |
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MPC5125 Microcontroller Data Sheet, Rev. 4
Electrical and Thermal Characteristics
Freescale Semiconductor
48
1. The SYS_XTAL_IN frequency, Sys PLL, and Core PLL settings must be chosen so that the resulting e300 clk, csb_clk, and
MCK frequencies do not exceed their respective maximum or minimum operating frequencies.
2. The values are valid for the user-operation mode. There can be deviations for test modes.
3. When selecting the peripheral clock frequencies, care needs to be taken about requirements for baud rates and minimum
frequency limitation.
4.The DDR data rate is 2x the DDR memory bus frequency.
SYS_XTAL_IN is the input clock multiplied by the system phase-locked loop (Sys PLL) and the clock unit to create the coherent
system bus clock (csb_clk), the internal clock for the DDR controller (ddr_clk), and the clocks for the peripherals.The csb_clk
serves as the clock input to the e300 core. A second PLL inside the e300 core multiplies the csb_clk frequency to create the
internal clock for the e300 core (core_clk). The system and core PLL multipliers are selected by the SPMF and COREPLL fields
in the reset configuration word, which is loaded at power-on reset.
See the MPC5125 Reference Manual (MPC5125RM)
, for more information on the clock subsystem.
4.3.3
Resets
The MPC5125 has three reset pins:
PORESET — Power-on reset
HRESET — Hard reset
SRESET — Software reset
These signals are asynchronous I/O signals and can be asserted at any time. The input side uses a Schmitt trigger and requires
the same input characteristics as other MPC5125 inputs, as specified in Section 4.1, “DC Electrical Characteristics.”
As long as VDD is not stable the HRESET output is not stable.
The timing relationship can be seen in the following figures.
Table 18. Reset Rise / Fall Timing
Description
Min
Max
Unit
SpecID
PORESET1 fall time
NOTES:
1 Make sure that the PORESET does not carry any glitches. The MPC5125 has no
filter to prevent them from getting into the chip.
—1
ms
A3.4
PORESET rise time
—
1
ms
A3.5
HRESET2,3 fall time
2 HRESET and SRESET must have a monotonous rise time.
3 The assertion of HRESET becomes active at power-on reset without any
SYS_XTAL clock.
—1
ms
A3.6
HRESET rise time
—
1
ms
A3.7
SRESET fall time
—
1
ms
A3.8
SRESET rise time
—
1
ms
A3.9
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