參數(shù)資料
型號(hào): MPC5125YVN400
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 46/94頁(yè)
文件大?。?/td> 0K
描述: IC MCU 32BIT E300 324TEPBGA
標(biāo)準(zhǔn)包裝: 60
系列: MPC51xx
核心處理器: e300
芯體尺寸: 32-位
速度: 400MHz
連通性: CAN,EBI/EMI,以太網(wǎng),I²C,USB OTG
外圍設(shè)備: DMA,WDT
輸入/輸出數(shù): 64
程序存儲(chǔ)器類型: ROMless
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 1.08 V ~ 3.6 V
振蕩器型: 外部
工作溫度: -40°C ~ 125°C
封裝/外殼: 324-BBGA
包裝: 托盤
MPC5125 Microcontroller Data Sheet, Rev. 4
Electrical and Thermal Characteristics
Freescale Semiconductor
50
Figure 7. HRESET Behavior
Figure 8. SRESET Behavior
Table 19. Reset Timing
Symbol
Description
Value
(XTALI CLOCK)
SpecID
tPORHOLD
Time PORESET must be held low before a qualified reset occurs.
4 cycles
A3.10
tHRVAL
Time HRESET is asserted after a qualified reset occurs.
26810 cycles1
A3.11
tSRVAL
Time SRESET is asserted after assertion of HRESET.
21 cycles
A3.12
tEXEC
Time between SRESET assertion and first core instruction fetch.
4 cycles
A3.13
tS_POR_CONF
Reset configuration setup time before assertion of PORESET.
1 cycle
A3.14
XTALI CLOCK
PORESET
SRESET
HRESET
RST_CONF[31:0]
ADDR[31:0]
tSRVAL
tEXEC
tHRVAL
tHRHOLD
tHR_SR_Delay
no new fetch of the RST_CONF
XTALI CLOCK
PORESET
SRESET
HRESET
RST_CONF[31:0]
ADDR[31:0]
tEXEC
tSRMIN
tSRHOLD
no new fetch of the RST_CONF
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