參數(shù)資料
型號(hào)： MPC5125YVN400
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 70/94頁(yè)
文件大?。?/td> 0K
描述： IC MCU 32BIT E300 324TEPBGA
標(biāo)準(zhǔn)包裝： 60
系列： MPC51xx
核心處理器： e300
芯體尺寸： 32-位
速度： 400MHz
連通性： CAN，EBI/EMI，以太網(wǎng)，I²C，USB OTG
外圍設(shè)備： DMA，WDT
輸入/輸出數(shù)： 64
程序存儲(chǔ)器類型： ROMless
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 1.08 V ~ 3.6 V
振蕩器型： 外部
工作溫度： -40°C ~ 125°C
封裝/外殼： 324-BBGA
包裝： 托盤
MPC5125 Microcontroller Data Sheet, Rev. 4
Electrical and Thermal Characteristics
Freescale Semiconductor
72
4.3.12
CAN
The CAN functions are available as TX pins at normal IO pads and as RX pins at the VBAT domain. There is no filter for the
wakeup dominant pulse. Any high-to-low edge can cause wakeup, if configured.
4.3.13
I2C
This section specifies the timing parameters of the inter-integrated circuit (I2C) interface. Refer to the I2C bus specification.
Table 37. I2C Input Timing Specifications — SCL and SDA
Sym
Description
Min
Max
Units
SpecID
1
Start condition hold time
2
—
IP bus cycle1
NOTES:
1 Inter-peripheral clock is defined in the MPC5125 Reference Manual (MPC5125RM)
A18.1
2
Clock low time
8
—
IP bus cycle1
A18.2
4
Data hold time
0.0
—
ns
A18.3
6
Clock high time
4
—
IP bus cycle1
A18.4
7
Data setup time
0.0
—
ns
A18.5
8
Start condition setup time (for repeated start condition only)
2
—
IP bus cycle1
A18.6
9
Stop condition setup time
2
—
IP bus cycle1
A18.7
Table 38. I2C Output Timing Specifications — SCL and SDA 1
NOTES:
1 Output timing is specified at a nominal 50 pF load.
Sym
Description
Min
Max
Units
SpecID
12
2 Programming IFDR with the maximum frequency results in the minimum output timings listed. The I2C interface is designed to
scale the data transition time, moving it to the middle of the SCL low period. The actual position is affected by the prescale and
division values programmed in IFDR.
Start condition hold time
6
—
IP bus cycle3
3 Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time that SCL or SDA
takes to reach a high level depends on external signal capacitance and pullup resistor values.
A18.8
22
Clock low time
10
—
IP bus cycle3
A18.9
34
4 Inter -peripheral Clock is defined in the MPC5125 Reference Manual (MPC5125RM).
SCL/SDA rise time
—
7.9
ns
A18.10
Data hold time
7
—
IP bus cycle3
A18.11
SCL/SDA fall time
—
7.9
ns
A18.12
Clock high time
10
—
IP bus cycle3
A18.13
Data setup time
2
—
IP bus cycle3
A18.14
Start condition setup time (for repeated start condition only)
20
—
IP bus cycle3
A18.15
Stop condition setup time
10
—
IP bus cycle3
A18.16
相關(guān)PDF資料
PDF描述
MPC533CVR40 IC MPU 512K FLASH 40MHZ 388-PBGA
MPC535CZP40 IC MCU 1M FLASH 40MHZ 388-BGA
MPC5534MVM80 MCU 1MB FLASH 80MHZ 208MAPBGA
MPC5553MVR132 MCU 1.5MB FLASH 132MHZ 416-PBGA
MPC555LFMZP40 IC MCU 32BIT 40MHZ 272-BGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MPC5125YVN400 制造商:Freescale Semiconductor 功能描述:ICMICROPROCESSOR32-BITCMOSPBGA324PI
MPC5125YVN400R 制造商:Freescale Semiconductor 功能描述:POWERPC EMBEDDED SOC - Tape and Reel
MPC5200 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Hardware Specifications
MPC5200B 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:SDRAM/DDR Memory Controller
MPC5200B_08 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:SDRAM / DDR Memory Controller
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*