參數(shù)資料
型號(hào)： MPC5125YVN400
廠商： Freescale Semiconductor
文件頁數(shù)： 47/94頁
文件大?。?/td> 0K
描述： IC MCU 32BIT E300 324TEPBGA
標(biāo)準(zhǔn)包裝： 60
系列： MPC51xx
核心處理器： e300
芯體尺寸： 32-位
速度： 400MHz
連通性： CAN，EBI/EMI，以太網(wǎng)，I²C，USB OTG
外圍設(shè)備： DMA，WDT
輸入/輸出數(shù)： 64
程序存儲(chǔ)器類型： ROMless
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 1.08 V ~ 3.6 V
振蕩器型： 外部
工作溫度： -40°C ~ 125°C
封裝/外殼： 324-BBGA
包裝： 托盤
Electrical and Thermal Characteristics
MPC5125 Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
51
4.3.4
External Interrupts
The MPC5125 provides three different kinds of external interrupts:
IRQ interrupts
GPIO interrupts with simple interrupt capability (not available in power-down mode)
Wakeup interrupts
IPIC inputs must be valid for at least tPICWID to ensure proper operation in edge-triggered mode.
4.3.5
SDRAM (DDR)
The MPC5125 memory controller supports these types of DDR devices:
DDR-1 (SSTL_2 class II interface)
DDR-2 (SSTL_18 interface)
LPDDR (1.8V I/O supply voltage)
SDR D-RAM
JEDEC standards define the minimum set of requirements for compliant memory devices:
JEDEC standard, DDR2 SDRAM specification, JESD79-2C, May 2006
JEDEC standard, Double Data Rate (DDR) SDRAM specification, JESD79E, May 2005
JEDEC standard, Low Power Double Data Rate (LPDDR) SDRAM specification, JESD79-4, May 2006
The MPC5125 supports the configuration of two output drive strengths for DDR2 and LPDDR:
Full drive strength
Half drive strength (intended for lighter loads or point-to-point environments)
The MPC5125 memory controller supports dynamic on-die termination in the host device and in the DDR2 memory device.
This section includes AC specifications for all DDR SDRAM pins. The DC parameters are specified in Section 4.1, “DC
tH_POR_CONF
Reset configuration hold time after assertion of PORESET.
1 cycle
A3.15
tHR_SR_DELAY
Time from falling edge of HRESET to falling edge of SRESET.
4 cycles
A3.16
tHRHOLD
Time HRESET must be held low before a qualified reset occurs.
4 cycles
A3.17
tSRHOLD
Time SRESET must be held low before a qualified reset occurs.
4 cycles
A3.18
tSRMIN
Time SRESET is asserted after it has been qualified.
1 cycles
A3.19
NOTES:
1 The timings will change when using the PLL lock detection circuit.
Table 20. IPIC Input AC Timing Specifications
Descriptions
Symbol
Min
Unit
Spec ID
IPIC inputs — minimum pulse width
tPICWID
2T
ns
A4.1
Table 19. Reset Timing (continued)
Symbol
Description
Value
(XTALI CLOCK)
SpecID
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