參數(shù)資料
型號(hào)： MPC5125YVN400
廠商： Freescale Semiconductor
文件頁數(shù)： 66/94頁
文件大?。?/td> 0K
描述： IC MCU 32BIT E300 324TEPBGA
標(biāo)準(zhǔn)包裝： 60
系列： MPC51xx
核心處理器： e300
芯體尺寸： 32-位
速度： 400MHz
連通性： CAN，EBI/EMI，以太網(wǎng)，I²C，USB OTG
外圍設(shè)備： DMA，WDT
輸入/輸出數(shù)： 64
程序存儲(chǔ)器類型： ROMless
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 1.08 V ~ 3.6 V
振蕩器型： 外部
工作溫度： -40°C ~ 125°C
封裝/外殼： 324-BBGA
包裝： 托盤
Electrical and Thermal Characteristics
MPC5125 Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
69
4.3.11
DIU
The DIU is a display controller designed to manage the TFT LCD display.
4.3.11.1
Interface to TFT LCD Panels, Functional Description
Figure 33 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure signals are shown with
positive polarity. The sequence of events for active matrix interface timing is:
DIU_CLK latches data into the panel on its positive edge (when positive polarity is selected). In active mode,
DIU_CLK runs continuously. This signal frequency could be from 5 to 66 MHz depending on the panel type.
DIU_HSYNC causes the panel to start a new line. It always encompasses at least one DIU_CLK pulse.
DIU_VSYNC causes the panel to start a new frame. It always encompasses at least one DIU_HSYNC pulse.
DIU_DE acts like an output enable signal to the LCD panel. This output enables the data to be shifted onto the display.
When disabled, the data is invalid and the trace is off.
Figure 33. Interface Timing Diagram for TFT LCD Panels
4.3.11.2
Interface to TFT LCD Panels, Electrical Characteristics
Figure 34 depicts the horizontal timing (timing of one line), including the horizontal sync pulse and the data. All parameters
shown in the diagram are programmable. This timing diagram corresponds to positive polarity of the DIU_CLK signal
(meaning the data and sync signals change at its rising edge) and active-high polarity of the DIU_HSYNC, DIU_VSYNC, and
DIU_DE signal. Signal polarity of DIU_HSYNC and DIU_VSYNC are selectable via the SYN_POL register, whether
active-high or active-low. The default is active-high. The DIU_DE signal is always active-high. Also, pixel clock inversion and
a flexible programmable pixel clock delay are also supported, programmed via the DIU Clock Config register (DCCR) in the
system clock module.
4 In card identification mode, card clock must be 100 kHz ~ 400 kHz, voltage ranges from 2.7 to 3.6 V.
5 Suggested Clock Period = T, CLK_DIVIDER (in SDHC Clock Rate register) = D, then TH = [(D + 1)/2] / (D + 1)
T where [] is
round.
DIU_LD[23:0]
DIU_CLK
DIU_DE
DIU_HSYNC
DIU_VSYNC
LINE 1
LINE 2
LINE 3
LINE 4
LINE n-1
LINE n
12
3
m-1
m
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