參數(shù)資料
型號(hào)： MN89305
廠商： PANASONIC CORP
元件分類： 顯示控制器
英文描述： 1024 X 768 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP144
封裝： 20 X 20 MM, PLASTIC, LQFP-144
文件頁(yè)數(shù)： 8/42頁(yè)
文件大?。?/td> 444K
代理商： MN89305
MN89305
LSIs for Display
16
s Electrical Characteristics
1. Absolute Maximum Ratings at VSS = VSSPLL = 0 V
Parameter
Symbol
Rating
Unit
Supply voltage
VDD
0.3 to +4.6
V
VDDPLL
5 V reference voltage 1
VREF5
0.3 to +5.7
V
Input pin voltage (except TYPE*)VI
0.3 to V
DD+0.3
V
Input pin voltage (TYPE-A)
VI5
0.3 to +6.0 2
V
Input pin voltage (TYPE-B)
VI
0.3 to V
DDPLL+0.3
V
Input pin voltage (TYPE-C)
VI5
0.3 to V
REF5+0.3
2
V
Output pin voltage (except TYPE*)VO
0.3 to V
DD+0.3
V
Output pin voltage (TYPE-C)
VO5
0.3 to V
REF5+0.3
2
V
Output current (TYPE-HL1)
IO
±3mA
Output current (TYPE-HL2)
IO
±6mA
Output current (TYPE-HL4)
IO
±12
mA
Output current (TYPE-HL8)
IO
±24
mA
Power dissipation
PD
700
mW
Operating temperature
Topr
0 to
+70
°C
Storage temperature
Tstg
55 to +150
°C
Note) 1. 1: The power application sequence must meet the following stipulations.
The periods t3-5 and t5-3 must be 0 or longer.
VDD and VREF5 must change smoothly.
If the periods t3-5 and t5-3 ever become negative, VREF5 VDD must be less than 3.6 V.
2: When VDD ≤ 1.4 V: 0.3 V to +4.6 V.
2. Type A pins:
A21, SA16 to SA19, AEN, IORD#, IOWR#, MEMR#, MEMW#, SBHE#, RESET
Type B pins:
PLLTEST
Type C pins:
A20, SA0 to SA15, SD0 to SD15, IOCS16#, MEMCS16#, IOCHRDY#, REFRESH#
Type HL1 pins: A20, MD0 to MD31, LCDON, BACKON, EXTCLK, LOGICON
Type HL2 pins: MA0 to MA9, SA0 to SA15, SD0 to SD15, WE#, CAS0# to CAS3#, RAS#
Type HL4 pins: FP, LD0 to LD7, LP, UD0 to UD7, SCK, DISP
Type HL8 pins: IOCS16#, MEMCS16#, IOCHRDY#, REFRESH#
3. The absolute maximum ratings are limiting values under which the chip will not be destroyed. Operation is not guaranteed
within these ranges.
4. All of the VDD, PLVDD, VSS, PLVSS, and VREF5 pins must connected directly, and by the shortest routes possible, to the
power supply or ground, respectively.
5. The crystal oscillator element used must be evaluated thoroughly in advance using the oscillator cell for this device.
6. Apply identical voltages to the VDD and PLVDD pins.
VDD
0 V
t3-5
VREF5 0 V
t5-3
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