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參數(shù)資料
| 型號： | MN89305 |
| 廠商： | PANASONIC CORP |
| 元件分類： | 顯示控制器 |
| 英文描述： | 1024 X 768 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP144 |
| 封裝： | 20 X 20 MM, PLASTIC, LQFP-144 |
| 文件頁數(shù)： | 7/42頁 |
| 文件大?。?/td> | 444K |
| 代理商： | MN89305 |
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LSIs for Display
MN89305
15
s Pin Descriptions (continued)
6) Chip Settings
Pin Name
I/O
Level
Function
RESET/RST
I
5 VTTL
RESET(ISA)/RST(386, 486, PCI)
When a high level is input to this pin, the chip is reset to its initial state. When 386
mode is used for the host type, this reset signal is also used for clock phase adjustment.
Note that this pin functions as an active-high signal.
MA[2 : 0]
I
CMOS
HOST type
These pins are set to input mode during the reset period. When these pins are in
input mode, they are used to decide the type of the connected host. Settings other
than those listed in the table are not permitted.
MA[2 : 0]
Host type
0
ISA
0
1
386SX
0
1
0
386DX
0
1
486
1
0
PCI
XIN/XO
I/O
CMOS
Clock In/Out
Chip clock input and output. Connect a crystal oscillator between these pins.
Since this clock is used as the display clock, the frequency of the input to these
pins determines the LCD panel refresh rate. The input frequency must be in the
range 4 MHz to 30 MHz.
EXTCLK
I
CMOS
External MCLK
The clock input to this pin is used as MCLK instead of the internal PLL oscillator.
If this clock starts during the reset period, the PLL circuit is automatically disabled
and this pin signal is used as MCLK. Input to this pin should be provided a clock
with a frequency that is in the range 35 MHz to 65 MHz and that is higher than
that of the XIN clock. This pin should be held at either VDD or VSS if this function
is unused.
MINTEST
I
CMOS
MINTEST pin must be held at VSS level during normal operation.
TEST[2 : 0]
I
5 VTTL
TEST[2:0] pins must be held at VSS during normal operation. (PCI mode only)
PLLTEST
I/O
Used for PLL testing. This pin must be held at the VSS level during normal
operation.
7) Power supply
Pin Name
I/O
Level
Function
VDD
Digital system power supply (3.3 V)
VSS
Digital system power supply (GND)
PLLVDD
PLL analog system power supply (3.3 V)
PLLVSS
PLL analog system power supply (GND)
VREF5
5 V input pin power supply (4.75 V to 5.25 V)
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