參數(shù)資料
型號: MN89305
廠商: PANASONIC CORP
元件分類: 顯示控制器
英文描述: 1024 X 768 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP144
封裝: 20 X 20 MM, PLASTIC, LQFP-144
文件頁數(shù): 4/42頁
文件大小: 444K
代理商: MN89305
MN89305
LSIs for Display
12
s Pin Descriptions (continued)
3) PCI Bus Related Pins (continued)
Due to the differences between the buses, the pin functions correspond as shown in the table.
PCI
386SX
386DX/486
ISA
FRAME
#
A22
AEN
CLK
CCLK
SBHE
#
C/BE0
#
BEL
#
BE0
#
IOWR
#
C/BE1
#
BEH
#
BE1
#
IORD
#
C/BE2
#
VSS
BE2
#
MEMW
#
C/BE3
#
A1
BE3
#
MEMR
#
IDSEL
A21
BIOSCS
#
A20
VSS
A[19 : 17]
SA[19 : 17]
IRDY
#
A16
SA16
AD[31 : 18]
A[15 : 2]
SA[15 : 2]
AD17
W/R
#
W/R
#
SA1
AD16
M/IO
#
M/IO
#
SA0
AD[15 : 0]
D[15 : 0]
SD[15 : 0]
PAR
ADS
#
ADS
#
REFRESH
#
TRDY
#
RDY
#
RDY
#
IOCHRDY
#
DEVSEL
#
LDEV
#
LDEV
#
MEMCS16
#
STOP#
BS16#
IOCS16#
4) Memory Access Related Pins
Pin Name
I/O
Level
Function
MA[9 : 0]
I/O
CMOS
Memory address
Display memory address.
These pins are set to input mode by a reset, and the pins MA[2:0] are used to set
the chip host type. The pins MA[9:3] are latched internally to the IC as the
expansion pin monitor register data.
RAS
#
O
RAS address strobe
Row address latch strobe signal.
CAS0
#
O
Lower CAS address strobe for RAM0
RAM0 low-order byte column address strobe signal.
CAS1
#
O
Upper CAS address strobe for RAM0
RAM0 high-order byte column address strobe signal.
CAS2
#
O
Lower CAS address strobe for RAM1
RAM1 low-order byte column address strobe signal.
CAS3
#
O
Upper CAS address strobe for RAM1
RAM1 high-order byte column address strobe signal.
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