參數(shù)資料
型號: MN89305
廠商: PANASONIC CORP
元件分類: 顯示控制器
英文描述: 1024 X 768 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP144
封裝: 20 X 20 MM, PLASTIC, LQFP-144
文件頁數(shù): 21/42頁
文件大?。?/td> 444K
代理商: MN89305
MN89305
LSIs for Display
28
No.
Descriptions
Min
Max
Unit
12
Delay time until TRDY# active
2
17
ns
13
Delay time until TRDY# inactive
2
13
ns
14
TRDY# high level to high-impedance state transition time
1
ns
15
Time until DEVSEL# active
2
15
ns
16
Time until DEVSEL# inactive
2
13
ns
17
DEVSEL# high level to high-impedance state transition time
1
ns
18
IRDY# setup time
7
ns
19
IRDY# hold time
2
ns
20
PAR (data parity) hold time
2
14
ns
21
PAR (data parity) valid output delay time
2
11
ns
s Electrical Characteristics (continued)
4. AC Characteristics (continued)
9) PCI Local Bus Timing
CLK = 33 MHz (continued)
Note) Values listed in the table apply when the external load capacitor is 10 pF. The output delay times will differ depending on
the external load capacitor.
No.
Descriptions
Min
Max
Unit
1
Time from STOP# high impedance to drive
2
15
ns
2
Time until STOP# active
2
16
ns
3
Delay time until STOP# inactive
2
14
ns
4
Time from STOP# high to high impedance
1
ns
10) PCI Local Bus STOP# Timing
CLK = 33 MHz
Note) Values listed in the table apply when the external load capacitor is 10 pF. The output delay times will differ depending on
the external load capacitor.
CLK
1
STOP
#
2
34
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