參數(shù)資料
型號: MN89305
廠商: PANASONIC CORP
元件分類: 顯示控制器
英文描述: 1024 X 768 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP144
封裝: 20 X 20 MM, PLASTIC, LQFP-144
文件頁數(shù): 19/42頁
文件大?。?/td> 444K
代理商: MN89305
MN89305
LSIs for Display
26
No.
Descriptions
Min
Max
Unit
1
A[23:2], M/IO#, BE[3:0]#, and W/R# setup time
15
ns
2
A[23:2], M/IO#, BE[3:0]#, and W/R# hold time
0
ns
3
ADS# setup time
15
ns
4
ADS# hold time
3
ns
5
BS16# active delay time
26
ns
6
BS16# inactive delay time
26
ns
7
BS16# high-level output time
15
ns
8
CPU write data setup time
6
ns
9
CPU write data hold time
0
ns
10
CPU read data setup time
4CLK
40
ns
11
CPU read data output off delay time
2
21
ns
12
RDY# setup time
2CLK
23
ns
13
RDY# hold time
2
ns
14
RDY# high-level output time
CLK
ns
15
CPU write wait time
2CLK
ns
16
CPU read wait time
4CLK
ns
17
LDEV# active delay time
26
ns
18
LDEV# inactive delay time
26
ns
s Electrical Characteristics (continued)
4. AC Characteristics (continued)
8) 386CPU Local Bus Timing
Note) 1. : The wait time differs depending on the chip status.
2. CLK in the table refers to one clock period of CCLK.
3. Values listed in the table apply when the external load capacitor is 50 pF. The output delay times will differ depending on
the external load capacitor.
CCLK1
(Internal)
CCLK
LDEV
#
D[15 : 0]
RDY
#
W/R
#
ADS
#
BS16
#
CPU WRITE
CPU READ
A[23 : 2]
M/IO
#
BE[3 : 0]
#
1
2
1
9
8
10
11
12
14
13
16
15
5
17
18
34
2
7
6
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