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參數(shù)資料
| 型號(hào)： | MN89305 |
| 廠商： | PANASONIC CORP |
| 元件分類： | 顯示控制器 |
| 英文描述： | 1024 X 768 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP144 |
| 封裝： | 20 X 20 MM, PLASTIC, LQFP-144 |
| 文件頁(yè)數(shù)： | 2/42頁(yè) |
| 文件大?。?/td> | 444K |
| 代理商： | MN89305 |
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MN89305
LSIs for Display
10
s Pin Descriptions (continued)
2) ISA Bus Related Pins (continued)
Pin Name
I/O
Level
Function
SBHE
#
I
5 V TTL
System byte high enable
Indicates how the 16-bit bus is being used.
SBHE SAO
Bus status
0
16-bit transfer
01
High-order byte transfer
10
Low-order byte transfer
1
Disabled
IOWR
#
I
5 V TTL
I/O write
Indicates an I/O write request.
IORD
#
I
5 V TTL
I/O read
Indicates an I/O read request.
MEMW
#
I
5 V TTL
Memory write
Indicates a memory write request.
MEMR
#
I
5 V TTL
Memory read
Indicates a memory read request.
A[21 : 20]
I
5 V TTL
Address[21 : 20]
Address bits 20 and 21.
SA[19 : 0]
I
5 V TTL
Address[19 : 0]
Address bits 0 to 19
SD[15 : 0]
I
5 V TTL
Data[15 : 0]
Host bus data bus pins
IOCHRDY
#
O
I/O channel ready
This pin outputs either a low level or a high-impedance state. It goes to the low
level when a wait is applied to either an I/O or memory access.
MEMCS16
#
O
Memory chip select 16
This pin outputs either a low level or a high-impedance state. A low-level output
from this pin for a memory access to this chip informs the system that 16-bit
transfers are possible for this memory access. Note that 16-bit transfers are always
possible for accesses to display memory.
IOCS16
#
O
I/O chip select 16
This pin outputs either a low level or a high-impedance state. A low-level output
from this pin for an I/O access to this chip informs the system that 16-bit transfers
are possible for this I/O access.
REFRESH
#
I
5 V TTL
Refresh
A low level input to this pin indicates the timing for DRAM refresh. All memory
access requests issued when this input is low are ignored.
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