參數(shù)資料
型號: MN89305
廠商: PANASONIC CORP
元件分類: 顯示控制器
英文描述: 1024 X 768 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP144
封裝: 20 X 20 MM, PLASTIC, LQFP-144
文件頁數(shù): 31/42頁
文件大?。?/td> 444K
代理商: MN89305
LSIs for Display
MN89305
37
LP
FP
LD[7 : 0]
Line 479
Line 480
Line 1
1
Line 2
Line 3
Line 4
Line 5
SCK
LD[7 : 0]
FP
LP
6
78
910
23
4
5
s Electrical Characteristics (continued)
4. AC Characteristics (continued)
20) Monochrome STN Single-Screen Panel Tming (8-bit data transfer mode)
Note) 1. 1: When the LP pulse width is specified to be 1 by LCD4 and LCD5.
2: When the number of characters on one line is set to be 84 characters by LCD0.
3: When the time from display completion to LP generation is set to be 1 character by LCD1 and LCD4.
4: When the time from LP completion to the 1 line completion is set to be 1 character by LCD5 and LCD0.
2. CLK is the display system clock (DCLK).
3. Values listed in the table apply when the external load capacitor is 30 pF.
No.
Descriptions
Min
Max
Unit
1
LP high-level period
8CLK
51
ns
2
FP rise to LP fall setup time
664CLK
102
ns
3
LP fall to FP fall hold time
8CLK
104
ns
4
DCLK fall to LP fall setup time
22CLK
103
ns
5
LP fall to SCK fall hold time
10CLK
104
ns
6
SCL high-level period
2CLK
5
ns
7
SCK low-level period
6CLK
5
ns
8
SCK period
8CLK
ns
9
LD[7:0] setup time
2CLK
10
ns
10
LD[7:0] hold time
6CLK
10
ns
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