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參數(shù)資料
| 型號： | MN89305 |
| 廠商： | PANASONIC CORP |
| 元件分類： | 顯示控制器 |
| 英文描述： | 1024 X 768 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP144 |
| 封裝： | 20 X 20 MM, PLASTIC, LQFP-144 |
| 文件頁數(shù)： | 16/42頁 |
| 文件大小： | 444K |
| 代理商： | MN89305 |
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LSIs for Display
MN89305
23
No.
Descriptions
Min
Max
Unit
5
A[21:20], SA[19:0], and SBHE# setup time
20
ns
6
A[21:20], SA[19:0], and SBHE# hold time
10
ns
7
IOWR#, IORD#, MEMW#, and MEMR# low-level period
2MCLK
+10
ns
8
IOWR#, IORD#, MEMW#, and MEMR# command inactive time
4MCLK
+10
ns
2
9
IOWR#, IORD#, MEMW#, and MEMR# low to IOCHRDY# delay time
25
ns
10
IOCHRDY# low-level period
0
1
ns
11
SD[15:0] setup time when IOWR# and MEMW# are active
20
ns
12
SD[15:0] hold time when IOWR# and MEMW# are active
10
ns
13
SD[15:0] delay time after IOCHRDY# goes to the high-impedance state
0ns
when IOWR# and MEMW# are active
14
SD[15:0] hold time when IOWR# and MEMW# are active
2
30
ns
15
MEMCS16# active delay time after A[21:20] and SA[19:16]
25
ns
16
MEMCS16# inactive delay time after A[21:20] and SA[19:16]
25
ns
17
IOCS16# active delay time after SA[15:0]
25
ns
18
IOCS16# inactive delay time after SA[15:0]
25
ns
s Electrical Characteristics (continued)
4. AC Characteristics (continued)
3) ISA Timing (continued)
Note) 1. 1: Differs depending on the operating mode.
2: 7 MCLK inactive periods are required for MEMW# and MEMR# after word writes to GR06, SR08, SR0D, and
SR15.
7 MCLK inactive periods are required for IOWR# and IORD# after word writes to CR1A.
20 MCLK inactive periods are required for MEMW# and MEMR# after word writes to SR07.
2. MCLK in the table refers to one clock period of the memory clock.
3. Values listed in the table apply when the external load capacitor is 50 pF. The output delay times will differ depending on
the external load capacitor.
4) CCLK Timing (local bus)
CCLK
3
12
No.
Descriptions
Min
Max
Unit
1
CCLK rise time
4ns
2
CCLK fall time
4ns
3
CCLK period (486 mode)
30 1
1
ns
3
CCLK period (386 mode)
15 2
2
ns
Note) 1. 1: CCLK must meet the following condition: (MCLK
+ 5) < CCLK < (4 × MCLK) 5
2: CCLK must meet the following condition: (MCLK/2)
+ 5 < CCLK < (MCLK × 2) 5
2. MCLK refers to one clock period of the memory clock.
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