參數(shù)資料
型號(hào)： MN89305
廠商： PANASONIC CORP
元件分類： 顯示控制器
英文描述： 1024 X 768 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP144
封裝： 20 X 20 MM, PLASTIC, LQFP-144
文件頁數(shù)： 6/42頁
文件大?。?/td> 444K
代理商： MN89305
MN89305
LSIs for Display
14
s Pin Descriptions (continued)
5) LCD Related Pins (continued)
Pin Name
I/O
Level
Function
DISP
O
Display enable
Display enable signal output to the LCD. This output is used as the blanking
signal in external RAMDAC mode and as the display enable signal when a TFT
LCD panel is used.
SCK
O
Shift clock
Data shift clock output to an STN LCD panel. This output is used as the dot clock
output for a TFT LCD panel or in external RAMDAC mode.
UD[7 : 0]
O
Upper/Lower data 7 : 0
LD[7 : 0]
Display data outputs.
In external RAMDAC mode LD[7:0] are used as the display data and UD[0:7] are
used as the write data lines to the RAMDAC register.
The table below shows the pin functions for each panel type.
Pin
TFT
STN(1S)
STN(2S)
External RAMDAC
DISP
DEN
DISP
BLANK
LP
HSYNC
LP
HSYNC
FP
VSYNC
FP
VSYNC
SCK
DCLK
SCK
DCLK
UD7
R4
UD7
WD7
UD6
R3
UD6
WD6
UD5
R2
UD5
WD5
UD4
R1
UD4
WD4
UD3
R0
UD3
WD3
UD2
G5
UD2
WD2
UD1
G4
UD1
WD1
UD0
G3
UD0
WD0
LD7
G2
LD7
P7
LD6
G1
LD6
P6
LD5
G0
LD5
P5
LD4
B4
LD4
P4
LD3
B3
LD3
P3
LD2
B2
LD2
P2
LD1
B1
LD1
P1
LD0
B0
LD0
P0
Note) 1. The pins marked with a dash (
) in the table are set to the output state, and therefore should be left open.
2. In external RAMDAC mode, WD[7:0] are used as write data to the external RAMDAC register.
相關(guān)PDF資料
PDF描述
MN89306 800 X 600 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP128
MP1322-017LF 50 V, SILICON, PIN DIODE
MP4212 5 A, 60 V, 0.32 ohm, 2 CHANNEL, N AND P-CHANNEL, Si, POWER, MOSFET
MP4212 5 A, 60 V, 0.32 ohm, 4 CHANNEL, N AND P-CHANNEL, Si, POWER, MOSFET
MP6404 5 A, 60 V, 0.32 ohm, 6 CHANNEL, N AND P-CHANNEL, Si, POWER, MOSFET
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