參數(shù)資料
型號(hào)： MN89305
廠商： PANASONIC CORP
元件分類(lèi)： 顯示控制器
英文描述： 1024 X 768 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP144
封裝： 20 X 20 MM, PLASTIC, LQFP-144
文件頁(yè)數(shù)： 23/42頁(yè)
文件大?。?/td> 444K
代理商： MN89305
LSIs for Display
MN89305
3
s Function Block Descriptions
1) Host interface
The host interface decodes the host bus addresses, generates the I/O and memory access enable signals, and transfers
to the chip internal blocks required information for register read and write operations and for memory read and write
operations. Data transfers are performed in 16-bit units for the ISA, 386, and 486 buses, and performed in 32-bit units
for the PCI bus.
Host bus type
Data bus width
ISA
16 bits
386SX, 486, VL
16 bits
PCI
32 bits
Furthermore, since the MN89305 supports linear addressing, the CPU address calculation time can be reduced.
Thus memory accesses are faster than if memory were accessed using a VGA compatible address area.
When the PCI interface is used, only burst transfers are supported for memory transfers. I/O bus transfers must not
be done. These burst transfers to memory can be performed only when addresses are incremented linearly.
Note) 1. ISA bus is a registered trademark of the (US) Industry Standards Architecture.
2. VL bus is a registered trademark of the (US) Video Electronics Standard Association.
3. PCI bus is a registered trademark of the (US) Peripheral Component Interconnect Association.
4. VGA is a registered trademark of International Business Machines, Inc.
2) Write FIFO
The write FIFO provides a function that temporarily accumulates memory write requests from the CPU bus, and
thus significantly increases the speed with which the LSI can handle CPU bus memory write requests. The FIFO can
hold either 4 or 16 units of 32-bit data. This buffer compensates for the periods when the LSI cannot accept CPU
memory access requests, thus significantly reducing the wait time associated with CPU memory writes.
3) Read FIFO
When the LSI receives a memory read request from the CPU, the LSI loads data from consecutive memory addresses
starting at the address requests by the CPU into the read FIFO. This allows the LSI to quickly output data if the CPU
issues memory read requests for consecutive addresses. If the CPU issues a request for data at an address not stored in
the FIFO, the data in the FIFO is all invalidated and then data from that new address is read out. The read FIFO can be
used in graphics modes that use 256 or more colors.
4) Graphics controller
The graphics controller processes data from the write FIFO according to the mode specified by the current register
settings. According to the operating mode, this module performs data expansion processing on the data from the write
FIFO and then the resultant data is sent to the memory access arbitrator. Furthermore, according to the operating mode,
this module processes data read from memory and then sends the resultant data to the host interface.
5) Memory access arbitrator
The memory access arbitrator arbitrates memory access requests from the BitBLT block, display data read requests
from the LCD controller, and memory access requests from the half frame controller. It then sends the memory access
request, address, and data to the memory interface.
相關(guān)PDF資料
PDF描述
MN89306 800 X 600 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP128
MP1322-017LF 50 V, SILICON, PIN DIODE
MP4212 5 A, 60 V, 0.32 ohm, 2 CHANNEL, N AND P-CHANNEL, Si, POWER, MOSFET
MP4212 5 A, 60 V, 0.32 ohm, 4 CHANNEL, N AND P-CHANNEL, Si, POWER, MOSFET
MP6404 5 A, 60 V, 0.32 ohm, 6 CHANNEL, N AND P-CHANNEL, Si, POWER, MOSFET
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