參數(shù)資料
型號: MN89305
廠商: PANASONIC CORP
元件分類: 顯示控制器
英文描述: 1024 X 768 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP144
封裝: 20 X 20 MM, PLASTIC, LQFP-144
文件頁數(shù): 24/42頁
文件大?。?/td> 444K
代理商: MN89305
MN89305
LSIs for Display
30
s Electrical Characteristics (continued)
4. AC Characteristics (continued)
13) Memory Access Timing (setup procedure)
This LSI allows the timing with which DRAM is accessed to be adjusted by setting the memory control expansion
registers SR0F and SR11. Set up the optimal cycle timing for the specifications of the DRAM actually used.
1. When fast page mode DRAM is used
2. When EDO DRAM is used
Note) 1. T is one period of MCLK (the divided-by-2 PLL clock: 35 MHz to 65 MHz).
2. Ta: The delay time from RAS# low to CAS# low. This period can be set to a value in the range 2T to 5T.
Tb: The CAS# low-level period. This period can be set to a value in the range T to 2T.
Tc: The RAS# high-level period. This period can be set to a value in the range 2T to 5T.
3. Ta is set with memory control register 3 (SR11) bits 0 and 1.
Tb is set with memory control register 2 (SR0F) bit 1.
Tc is set with memory control register 3 (SR11) bits 4 and 5.
4. For fast page mode DRAM, the random access cycle will be Ta
+ Tb + Tc. (min.)
5. For EDO DRAM, the random access cycle will be Ta
+ Tb + Tc + T. (min.)
MCLK
RAS
#
CAS
#
T
Ta
Tb
Tc
MCLK
RAS
#
CAS
#
T
Ta
Tb
Tc
T
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