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參數(shù)資料
| 型號(hào)： | MESC-ST1 |
| 廠商： | Lineage Power |
| 英文描述： | Enhanced Services Controller，Statistics Monitor - 65535 Connections(可統(tǒng)計(jì)檢測65535個(gè)連接的增強(qiáng)型服務(wù)控制器) |
| 中文描述： | 增強(qiáng)服務(wù)控制器，統(tǒng)計(jì)監(jiān)測- 65535連接（可統(tǒng)計(jì)檢測65535個(gè)連接的增強(qiáng)型服務(wù)控制器） |
| 文件頁數(shù)： | 9/31頁 |
| 文件大?。?/td> | 182K |
| 代理商： | MESC-ST1 |
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August 2000
MESC_ST1
MACRO
Data Sheet
Logic Design Solutions
9/28
The micro must store in the IE_SDRAM the (1/Contract_PCR) value in units of timeslots (680ns) per connection.
1.4.2.5
Architecture of the second set
The process of the second set of statistics
is done with the help of the IE_SDRAM. The IE_SDRAM holds all the
neccessary data fields for all the 65535 Channels for CLP 0 and CLP 1. The IE_SDRAM is used also as a connection
memory to identify which channel is processed.
During one timeslot (680 ns) all the statistics update of one channel is done and the read or the reset of the statistic of another
channel is also done.
When one match happen between the E.S.I. bus and the Connection Memory on a particular channel, all the statistic counters
of this channel are updated according E.S.I. data.
If one statistic counter roll over, one interruption is generated and one status interrupt register is updated to inform the CPU.
To reset all the statistic counters associated to one channel, the CPU should run first one read command of the statistic
counters and then run the reset command of the particular channel.
E.S.I. bus
CPU_Write
65535 Channels
IE
SDRAM
CPU_Read
Irq_ovf
FIFO_RD_RESET
FIFO_IN
FIFO_OUT
STAT.
UPDATE
LOGIC
INTERFACE
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