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參數(shù)資料
| 型號： | MESC-ST1 |
| 廠商： | Lineage Power |
| 英文描述： | Enhanced Services Controller，Statistics Monitor - 65535 Connections(可統(tǒng)計檢測65535個連接的增強(qiáng)型服務(wù)控制器) |
| 中文描述： | 增強(qiáng)服務(wù)控制器，統(tǒng)計監(jiān)測- 65535連接（可統(tǒng)計檢測65535個連接的增強(qiáng)型服務(wù)控制器） |
| 文件頁數(shù)： | 5/31頁 |
| 文件大?。?/td> | 182K |
| 代理商： | MESC-ST1 |
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August 2000
MESC_ST1
MACRO
Data Sheet
Logic Design Solutions
5/28
1.3
Pin Description
Signal
RESETN
CK50
CK_SDRAM
LBUS_CK16
Direction
Input
Input
Input
Input
Activity
Low
R edge
R edge
R edge
Description
FPGA system asynchronous reset.
ESI clock. Must be connected to APC ESCLK signal.
SDRAM clock. Must be connected to SDRAM input clock signal.
CPU clock.
LBUS_CSN
LBUS_ADSN_ALE
LBUS_WRN
LBUS_RDN
LBUS_AD(31:0)
LBUS_RDYN
LBUS_IRQN
Input
Input
Input
Input
Low
High
Low
Low
High
Low
Low
FPGA chip select.
FPGA address latch enable.
FPGA write.
FPGA read.
FPGA address/data lines.
FPGA acknowledges write or read data.
FPGA interruption in case of overflow.
Input/output
output
output
ESC_SYNC
Input
High
FPGA synchronisation pulse. Must be connected to APC ESSYNC
signal.
FPGA ESC data. Must be connected to APC ESTXD signal.
ESC_TXD(15:0)
Input
High
IE_RAS
IE_CAS
IE_WE
IE_DQML
IE_DQMU
IE_BA(1:0)
IE_AD_SDRAM(11:
0)
IE_DQ(15:0)
output
output
output
output
output
output
output
Low
Low
Low
Low
Low
-
-
RAS signal of the IE_SDRAM..
CAS signal of the IE_SDRAM..
WE signal of the IE_SDRAM..
DQML signal of the IE_SDRAM..
DQMU signal of the IE_SDRAM..
BA signal of the IE_SDRAM..
BA signal of the IE_SDRAM..
Input/output
-
Data signal of the IE_SDRAM..
E_RAS
E_CAS
E_WE
E_DQML
E_DQMU
E_BA(1:0)
output
output
output
output
output
output
output
Low
Low
Low
Low
Low
-
-
RAS signal of the E_SDRAM..
CAS signal of the E_SDRAM..
WE signal of the E_SDRAM..
DQML signal of the E_SDRAM..
DQMU signal of the E_SDRAM..
BA signal of the E_SDRAM..
BA signal of the E_SDRAM..
E_AD_SDRAM(11:0
)
E_DQ(15:0)
Input/output
-
Data signal of the E_SDRAM..
PLL_IN
PLL_OUT
Input
output
-
-
PLL input 50MHz. Must be connected to APC ESCLK signal.
PLL output 100MHz. Must be connected to SDRAM input clock signal.
PROBEA(31:0)
PROBEB(3:0)
output
output
-
-
For debug purpose.
For debug purpose.
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