
August 2000
MESC_ST1
MACRO
Data Sheet
Logic Design Solutions
16/28
The VCX_CLP Register must be modified only when any E_IE Command has been completed.
1.6.2.2
Data Register
Address = 0004\h.
Write only.
The Data Register is used by the CPU to program the Contract_PCR and the Contract_SCR associated to each Channel.
It is also used to activate of inactivate one channel (see E_IE Command_Register).
This is done through the use of the VCX_CLP Register and the E_IE Command Register.
BIT
31:0
DESCRIPTION
Data.
The Data will be processed as the Contract_PCR if the E_IE Command Register(3:1) = 011.
The Data will be processed as the Contract_SCR if the E_IE Command Register(3:1) = 010.
The Data Register must be modified only when any E_IE Command has been completed.
1.6.2.3
E_IE
Command Register
Address = 0008\h.
Read / Write.
The E_IE Command Register enables the CPU to manage the statistics processed in the IE_SDRAM and in the E_SDRAM.
BIT
0
DESCRIPTION
Execute one command for IE_SDRAM:
1 : Execute the command determined by bit (3:1) for IE_SDRAM
0 : IE_SDRAM Command done
Determination of the command for IE_SDRAM :
000 : Inactivate Channel (Channel number provided in VCX_CLP Register – CLP must be at 0)
001 : Activate Channel (Channel number provided in VCX_CLP Register – CLP must be at 0)
010 : Write Contract_SCR (Channel and CLP number provided in VCX_CLP Register)
011 : Write Contract_PCR (Channel and CLP number provided in VCX_CLP Register)
100 : Read one set of statistics processed by IE_SDRAM
101 : Reset one set of statistics processed by IE_SDRAM
110 : Reserved
111 : Reserved
3:1
4
Execute one command for E_SDRAM:
1 : Execute the command determined by bit (6:5) for E_SDRAM
0 : E_SDRAM Command done
Determination of the command for E_SDRAM :
00 : Inactivate Channel (Channel number provided in VCX_CLP Register – CLP must be at 0)
01 : Activate Channel (Channel number provided in VCX_CLP Register – CLP must be at 0)
10 : Read and Reset (e_stat) statistic determined by bit (10:7) processed by E_SDRAM
11 : Reserved
Determination of the statistic to be read and reset in E_SDRAM :
0000 : e_stat_0 0101 : e_stat_5
0001 : e_stat_1 0110 : e_stat_6
0010 : e_stat_2 0111 : e_stat_7
0011 : e_stat_3 1000 : e_stat_8
0100 : e_stat_4 1001 : e_stat_9
6:5
10:7