參數(shù)資料
型號： MESC-ST1
廠商： Lineage Power
英文描述： Enhanced Services Controller，Statistics Monitor - 65535 Connections(可統(tǒng)計檢測65535個連接的增強型服務(wù)控制器)
中文描述： 增強服務(wù)控制器，統(tǒng)計監(jiān)測- 65535連接（可統(tǒng)計檢測65535個連接的增強型服務(wù)控制器）
文件頁數(shù)： 2/31頁
文件大?。?/td> 182K
代理商： MESC-ST1
August 2000
MESC_ST1
MACRO
Data Sheet
Logic Design Solutions
2/28
1.
Description................................................................................................................................................................................................4
1.1
Implementation example....................................................................................................................................................................4
1.2
Symbol...................................................................................................................................................................................................4
1.3
Pin Description...................................................................................................................................................................................5
1.4
Functionnal Description....................................................................................................................................................................6
1.4.1
The first set of statistics ..........................................................................................................................................................6
1.4.2
The second set of statistics ....................................................................................................................................................7
1.4.2.1
Minimum and Maximum Period CLP P..............................................................................................................................7
1.4.2.2
Ingress Peak Cell Rate CLP P and Cell Delay Variation CLP P......................................................................................7
1.4.2.3
Ingress Sustained Cell Rate Violation Count CLP P.......................................................................................................8
1.4.2.4
Ingress Maximum Burst Size CLP P..................................................................................................................................8
1.4.2.5
Architecture of the second set..........................................................................................................................................9
1.4.3
The third set of statistics.......................................................................................................................................................10
1.4.3.1
Architecture of the third set.............................................................................................................................................11
1.5
E.S.I. interface..................................................................................................................................................................................12
1.6
Statistics Monitor Register...........................................................................................................................................................15
1.6.1
Register Address Map...........................................................................................................................................................15
1.6.2
Registers...................................................................................................................................................................................15
1.6.2.1
VCX_CLP Register............................................................................................................................................................15
1.6.2.2
Data Register......................................................................................................................................................................16
1.6.2.3
E_IE Command Register...................................................................................................................................................16
1.6.2.4
PHY Command Register....................................................................................................................................................19
1.6.2.5
PHY Port Register..............................................................................................................................................................19
1.6.2.6
IE Read_Reset_FIFO Register.........................................................................................................................................20
1.6.2.7
One Second Register........................................................................................................................................................20
1.6.2.8
Mask IRQ Overflow Register...........................................................................................................................................21
1.6.2.9
PHY Stat_0 and Stat_1 Register......................................................................................................................................21
1.6.2.10
IRQ Overflow Status Register....................................................................................................................................22
1.6.2.11
PHY address Overflow Register.................................................................................................................................22
1.6.2.12
IE_STAT address Overflow Register........................................................................................................................22
1.6.2.13
E_Read_Reset Register...............................................................................................................................................23
1.6.2.14
E_STAT address Overflow Register.........................................................................................................................23
1.6.2.15
E_STAT Configuration Register................................................................................................................................24
1.7
Write cycle........................................................................................................................................................................................25
1.8
Read cycle..........................................................................................................................................................................................25
1.9
FPGA Timing....................................................................................................................................................................................26
1.10
CPU interface..............................................................................................................................................................................26
1.11
APC interface..............................................................................................................................................................................26
1.12
SDRAM interface.......................................................................................................................................................................26
1.13
SDRAM Device used..................................................................................................................................................................26
1.14
FPGA Configuration..................................................................................................................................................................26
1.15
Pin-Out.........................................................................................................................................................................................27
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