參數(shù)資料
型號(hào)： MESC-ST1
廠商： Lineage Power
英文描述： Enhanced Services Controller，Statistics Monitor - 65535 Connections(可統(tǒng)計(jì)檢測(cè)65535個(gè)連接的增強(qiáng)型服務(wù)控制器)
中文描述： 增強(qiáng)服務(wù)控制器，統(tǒng)計(jì)監(jiān)測(cè)- 65535連接（可統(tǒng)計(jì)檢測(cè)65535個(gè)連接的增強(qiáng)型服務(wù)控制器）
文件頁(yè)數(shù)： 10/31頁(yè)
文件大?。?/td> 182K
代理商： MESC-ST1
August 2000
MESC_ST1
MACRO
Data Sheet
Logic Design Solutions
10/28
The IE_SDRAM address memory is organised as the following :
22 downto 7
6 downto 5
4
3 downto 0
IE_VCX field
coming from
E.S.I. bus
Or from VCX_CLP
Register.
0000\h to FFFE\h.
Gives 65535 possible
Channels.
Fixed to ‘00’
CLP field
coming from
E.S.I. bus
Or from VCX_CLP
Register.
0 or 1.
0000 : Channel number, 0000\h to FFFE\h.
0001 : Previous_arrival_time_low
0010 : Previous_arrival_time_high
0011 : Minimum_Period_low
0100 : Minimum_Period_high
0101 : Maximum_Period_low
0110 : Maximum_Period_high
0111 : 1/Contract_SCR_low
1000 : 1/Contract_SCR_high
1001 : Previous_violation_time_low
1010 : Previous_violation time_high
1011 : SCR_violation
1100 : 1/Contract_PCR_low
1101 : 1/Contract_PCR_high
1110 : Maximum_Burst_Size
1111 : Current_Burst_Size
All data are 16-bits wide. So the SDRAM required is a 8Meg x 16, which is a very standard device.
All SDRAM accesses are under control of one state machine. It manages SDRAM initialisation and refresh, as well as CPU
access and statistics update.
1.4.3
The third set of statistics
The third set is composed of the following statistics :
Ingress Received Cells CLP
P
(for convenience called – e_stat_0)
Egress Transmitted Cells CLP
P
(for convenience called - e_stat_1)
Ingress Sustained Cell Rate CLP
P
(for convenience called - e_stat_2)
Ingress Cells Discarded due to Buffer management CLP
P
(for convenience called - e_stat_3)
Ingress Cells Discarded due to Policing CLP
P
(for convenience called - e_stat_4)
Ingress Frames Discarded due to Buffer management CLP
P
(for convenience called - e_stat_5)
Ingress Frames Discarded due to Policing CLP
P
(for convenience called - e_stat_6)
Ingress Cells Tagged due to Policing (for convenience called - e_stat_7)
Egress Cells Discarded due to Buffer management CLP
P
(for convenience called - e_stat_8)
Egress Frames Discarded due to Buffer management CLP
P
(for convenience called - e_stat_9)
These statistics are managed with the help of the E_SDRAM component.
This Ingress Sustained Cell Rate CLP
P
16-bits counter (e_stat_2) requires the use of a one second pulse timing reference.
This statistic maintain the count of number of cells received in a one second period. Start of one second period is triggered
by the micro, and is reset by the FPGA after one second.
The e_stat_0 and e_stat_1 counters are 32-bits free running counter, all other counters are free running 16-bits counter.
Note :
e_stat_7 is not CLP dependant, thus, the CLP bit in the VCX_CLP Register should be always at 0 for this statistic.
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