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參數(shù)資料
| 型號： | MESC-ST1 |
| 廠商： | Lineage Power |
| 英文描述： | Enhanced Services Controller，Statistics Monitor - 65535 Connections(可統(tǒng)計檢測65535個連接的增強型服務控制器) |
| 中文描述： | 增強服務控制器，統(tǒng)計監(jiān)測- 65535連接（可統(tǒng)計檢測65535個連接的增強型服務控制器） |
| 文件頁數(shù)： | 25/31頁 |
| 文件大小： | 182K |
| 代理商： | MESC-ST1 |
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August 2000
MESC_ST1
MACRO
Data Sheet
Logic Design Solutions
25/28
1.7
Write cycle
The following chronogram describes the write cycle :
All the Cpu signals are synchronised with the Lbus_ck16 clock signal.
The Lbus_wrn, Lbus_rdn, Lbus_adsn_ale and Lbus_ad signals are only valid when the Lbus_csn signal is active low. The
Lbus_csn, Lbus_wrn, Lbus_rdn and Lbus_ad signals should stay stable until the Lbus_rdyn signal goes low.
When the Lbus_rdyn signal goes low, it means the data has been written in the FPGA.
The Lbus_adsn_ale signal is used by the FPGA to indentify the address phase of the Lbus_ad signals.
When the Lbus_wrn signals goes low, it means it is a write cycle.
1.8
Read cycle
The following chronogram describes the read cycle :
All the Cpu signals are synchronised with the Lbus_ck16 clock signal.
The Lbus_wrn, Lbus_rdn, Lbus_adsn_ale and Lbus_ad signals are only valid when the Lbus_csn signal is active low. The
Lbus_csn, Lbus_wrn, and Lbus_rdn signals should stay stable until the Lbus_rdyn signal goes low.
When the Lbus_rdyn signal goes low, it means the data has been read from the FPGA.
The Lbus_adsn_ale signal is used by the FPGA to indentify the address phase of the Lbus_ad signals.
When the Lbus_rdn signals goes low, it means it is a read cycle.
Lbus_ck16
Lbus_ad
Lbus_csn
Lbus_adsn_ale
Lbus_wrn
Lbus_rdn
Lbus_rdyn
Lbus_ck16
Lbus_ad
Lbus_csn
Lbus_adsn_ale
Lbus_wrn
Lbus_rdn
Lbus_rdyn
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